MMU question for PPC 603 - VxWorks

This is a discussion on MMU question for PPC 603 - VxWorks ; Following is an excerpt from the sysLib.c for PPC603 based BSP * * sysBatDesc[] is used to initialize the block address translation (BAT) * registers within the PowerPC e300 MMU. BAT hits take precedence * over Page Table Entry (PTE) ...

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Thread: MMU question for PPC 603

  1. MMU question for PPC 603

    Following is an excerpt from the sysLib.c for PPC603 based BSP

    *
    * sysBatDesc[] is used to initialize the block address translation
    (BAT)
    * registers within the PowerPC e300 MMU. BAT hits take precedence
    * over Page Table Entry (PTE) hits and are faster. Overlap of memory
    * coverage by BATs and PTEs is permitted in cases where either the
    IBATs
    * or the DBATs do not provide the necessary mapping (PTEs apply to
    both
    * instruction AND data space, without distinction).
    *
    * The primary means of memory control for VxWorks is the MMU PTE
    support
    * provided by vmLib and cacheLib. Use of BAT registers will conflict
    * with vmLib support. User's may use BAT registers for i/o mapping
    and
    * other purposes but are cautioned that conflicts with cacheing and
    mapping
    * through vmLib may arise. Be aware that memory spaces mapped
    through a BAT
    * are not mapped by a PTE and any vmLib() or cacheLib() operations on
    such
    * areas will not be effective, nor will they report any error
    conditions.
    *
    * Note: BAT registers CANNOT be disabled - they are always active.
    * For example, setting them all to zero will yield four identical
    data
    * and instruction memory spaces starting at local address zero, each
    128KB
    * in size, and each set as write-back and cache-enabled. Hence, the
    BAT regs
    * MUST be configured carefully.
    *
    * With this in mind, it is recommended that the BAT registers be used
    * to map LARGE memory areas external to the processor if possible.
    * If not possible, map sections of high RAM and/or PROM space where
    * fine grained control of memory access is not needed. This has the
    * beneficial effects of reducing PTE table size (8 bytes per 4k page)
    * and increasing the speed of access to the largest possible memory
    space.
    * Use the PTE table only for memory which needs fine grained (4KB
    pages)
    * control or which is too small to be mapped by the BAT regs.
    *
    * All BATs point to PROM/FLASH memory so that end customer may
    configure
    * them as required.
    *
    * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming
    Environments]
    */


    UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {

    ....


    My question is about the Note in the comments stating that the BATs
    can not be disabled and if all 0'ed they would yield 128K BAT at the
    top of the local memory. But what about the Vs/Vp bits. 0' ing BATS
    would set Vs and Vp bits to 0 and efeectively disable BATranslation.
    Am I missing smth?

    Onder

  2. Re: MMU question for PPC 603

    On Jul 22, 2:49 pm, onderya...@gmail.com wrote:
    > Following is an excerpt from the sysLib.c for PPC603 based BSP

    ....
    >
    > My question is about the Note in the comments stating that the BATs
    > can not be disabled and if all 0'ed they would yield 128K BAT at the
    > top of the local memory. But what about the Vs/Vp bits. 0' ing BATS
    > would set Vs and Vp bits to 0 and efeectively disable BATranslation.
    > Am I missing smth?


    Apparently, there have been PPC processors where it was true that
    disabling BATs didn't work.
    I have never actually used silicon that had that problem and I disable
    (i)BATs as you suggest.
    I often find myself not having a good reason to use all the iBATs --
    even when there are only 4 of them.
    dBATs however are precious resource and should be to the fullest
    extent possible.
    Use them to map large areas of PCI and/or flash space, it'll speed
    things up and use less RAM for page tables.

    Wind River has finally removed that nonsense from newer BSPs.
    A quick check of the vxWorks 6.6 BSP for mv6100 has a more accurate
    note.

    " * Note: BAT registers can be disabled if the VS and VP bits are both
    clear
    * in the upper BAT register of each pair. In the default
    configuration
    * (coded below) the VS and VP bits are cleared and thus the BAT
    registers
    * are disabled."

    HTH
    GV

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