Re: MMU question for PPC 603
On Jul 22, 2:49 pm, onderya...@gmail.com wrote:[color=blue]
> Following is an excerpt from the sysLib.c for PPC603 based BSP[/color]
> My question is about the Note in the comments stating that the BATs
> can not be disabled and if all 0'ed they would yield 128K BAT at the
> top of the local memory. But what about the Vs/Vp bits. 0' ing BATS
> would set Vs and Vp bits to 0 and efeectively disable BATranslation.
> Am I missing smth?[/color]
Apparently, there have been PPC processors where it was true that
disabling BATs didn't work.
I have never actually used silicon that had that problem and I disable
(i)BATs as you suggest.
I often find myself not having a good reason to use all the iBATs --
even when there are only 4 of them.
dBATs however are precious resource and should be to the fullest
Use them to map large areas of PCI and/or flash space, it'll speed
things up and use less RAM for page tables.
Wind River has finally removed that nonsense from newer BSPs.
A quick check of the vxWorks 6.6 BSP for mv6100 has a more accurate
" * Note: BAT registers can be disabled if the VS and VP bits are both
* in the upper BAT register of each pair. In the default
* (coded below) the VS and VP bits are cleared and thus the BAT
* are disabled."