vxworks kernel not booting when data cache is enabled - VxWorks

This is a discussion on vxworks kernel not booting when data cache is enabled - VxWorks ; Hi , I am working on PowerPC 7410 based SBC.I am able to boot the board with VxWorks2.2 kernel when i disable MMU(data and instruction cache).When i enable data cache (Torando IDE vxWorks components) i am unable to boot the ...

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Thread: vxworks kernel not booting when data cache is enabled

  1. vxworks kernel not booting when data cache is enabled

    Hi ,
    I am working on PowerPC 7410 based SBC.I am able to boot the
    board with VxWorks2.2 kernel when i disable MMU(data and instruction
    cache).When i enable data cache (Torando IDE vxWorks components) i am
    unable to boot the kernel.
    Is there any procedure to be followed when we enable data
    cache?What aspects can cause this problem?
    Thanks in advance
    Regards
    Nandakishore.

  2. Re: vxworks kernel not booting when data cache is enabled

    On Jun 24, 7:06*am, Nanda wrote:
    > Hi ,
    > * * * I am working on PowerPC 7410 based SBC.I am able to boot the
    > board with VxWorks2.2 kernel when i disable MMU(data *and instruction
    > cache).When i enable data cache (Torando IDE vxWorks components) i am
    > unable to boot the kernel.
    > * * * * * Is there any procedure to be followed when we enable data
    > cache?What aspects can cause this problem?
    > * * * *Thanks in advance
    > Regards
    > Nandakishore.


    Dear Nandakishore,

    Are you sure you use vxWorks 2.2 ? Maybe you use PID 2.2 ?
    I use vxWorks 6.5 and to solve this kind of problem I should set my
    sysBatDesc variable (located into sysLib.c). I don't know if this
    variable exist in 2.2.

    Good luck with this version.

    regards,
    Sylvain

  3. Re: vxworks kernel not booting when data cache is enabled

    Hi,

    Which BSP you are using is it in home developed or WRS.? Just check
    the Virtual Memory Mapping structure. Does it represents your Board
    description and requirement. Probably its not the problem with data/
    instruction cache but with MMU enabling/ Virtual to Physical memory
    mapping. As per my understanding there should be some control
    registers to enable and disable data/instruction cache and just enable
    MMU. Try to verify that..if you are able to boot without MMU then this
    should be the only problem.

    Best of luck.

    Thanks,
    Manish Gupta

    On Jun 24, 10:06 am, Nanda wrote:
    > Hi ,
    > I am working on PowerPC 7410 based SBC.I am able to boot the
    > board with VxWorks2.2 kernel when i disable MMU(data and instruction
    > cache).When i enable data cache (Torando IDE vxWorks components) i am
    > unable to boot the kernel.
    > Is there any procedure to be followed when we enable data
    > cache?What aspects can cause this problem?
    > Thanks in advance
    > Regards
    > Nandakishore.



  4. Re: vxworks kernel not booting when data cache is enabled

    On Jun 24, 1:06 am, Nanda wrote:
    > Hi ,
    > I am working on PowerPC 7410 based SBC.I am able to boot the
    > board with VxWorks2.2 kernel when i disable MMU(data and instruction
    > cache).When i enable data cache (Torando IDE vxWorks components) i am
    > unable to boot the kernel.
    > Is there any procedure to be followed when we enable data
    > cache?What aspects can cause this problem?


    These problems with enabling dcache are almost always due to improper
    memory mapping in sysPhysMemDesc and/or sysBatDesc.
    For devices and almost all PCI memory spaces, you need to map the
    address spaces as cache inhibited, guarded, etc.
    Assuming you are using a custom or customized BSP -- otherwise you
    probably wouldn't have this problem -- take a look at sysLib.c for a
    standard supported PPC BSP (sp74xx would be a good one).

    Look at how PCI spaces are defined, e.g.,

    {
    (void *) PCI_MSTR_ISA_IO_LOCAL_B,
    (void *) PCI_MSTR_ISA_IO_LOCAL_B,
    PCI_MSTR_ISA_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID | VM_STATE_WRITABLE |
    VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    Also look at other spaces, like flash.

    {
    (void *) FLASH_ADRS,
    (void *) FLASH_ADRS,
    FLASH_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID | VM_STATE_WRITABLE |
    VM_STATE_CACHEABLE_NOT
    },

    People sometimes try to map everything with BAT registers -- including
    RAM.
    Making maximum use of BAT registers is a good idea, but you need to be
    careful.
    This can cause problems with certain device drivers that use
    cacheDmaMalloc().

    In short, you need to understand your target memory map and realize
    that everything can't be cacheable.
    But everything will be cacheable if you enable dcache and haven't
    marked the appropriate spaces as inhibited.

    HTH
    GV


  5. Re: vxworks kernel not booting when data cache is enabled

    Nanda,

    GV has pointed out the most common cause of this failure already. If
    you find that you are marking the memory areas as cached/non-cached
    correctly, check the memory init sequence in your bootrom. RAMs have
    a particular sequence to init memory for burst modes (used when you
    enable cache). If that sequence is not correctly executed, non-burst
    transfers (which happen if cache is disabled) will be fine, but the
    moment you enable cache, unpredictable data is transferred to cache.

    HTH
    -


    On Jun 25, 5:57 pm, gvarndell wrote:
    > On Jun 24, 1:06 am, Nanda wrote:
    >
    > > Hi ,
    > > I am working on PowerPC 7410 based SBC.I am able to boot the
    > > board with VxWorks2.2 kernel when i disable MMU(data and instruction
    > > cache).When i enable data cache (Torando IDE vxWorks components) i am
    > > unable to boot the kernel.
    > > Is there any procedure to be followed when we enable data
    > > cache?What aspects can cause this problem?

    >
    > These problems with enabling dcache are almost always due to improper
    > memory mapping in sysPhysMemDesc and/or sysBatDesc.
    > For devices and almost all PCI memory spaces, you need to map the
    > address spaces as cache inhibited, guarded, etc.
    > Assuming you are using a custom or customized BSP -- otherwise you
    > probably wouldn't have this problem -- take a look at sysLib.c for a
    > standard supported PPC BSP (sp74xx would be a good one).
    >
    > Look at how PCI spaces are defined, e.g.,
    >
    > {
    > (void *) PCI_MSTR_ISA_IO_LOCAL_B,
    > (void *) PCI_MSTR_ISA_IO_LOCAL_B,
    > PCI_MSTR_ISA_IO_SIZE,
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE |
    > VM_STATE_MASK_GUARDED,
    > VM_STATE_VALID | VM_STATE_WRITABLE |
    > VM_STATE_CACHEABLE_NOT |
    > VM_STATE_GUARDED
    > },
    >
    > Also look at other spaces, like flash.
    >
    > {
    > (void *) FLASH_ADRS,
    > (void *) FLASH_ADRS,
    > FLASH_SIZE,
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE,
    > VM_STATE_VALID | VM_STATE_WRITABLE |
    > VM_STATE_CACHEABLE_NOT
    > },
    >
    > People sometimes try to map everything with BAT registers -- including
    > RAM.
    > Making maximum use of BAT registers is a good idea, but you need to be
    > careful.
    > This can cause problems with certain device drivers that use
    > cacheDmaMalloc().
    >
    > In short, you need to understand your target memory map and realize
    > that everything can't be cacheable.
    > But everything will be cacheable if you enable dcache and haven't
    > marked the appropriate spaces as inhibited.
    >
    > HTH
    > GV



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