DPIO2 MVME 5500 - VxWorks

This is a discussion on DPIO2 MVME 5500 - VxWorks ; hello, we are using tornado 2.2.1 and vxWorks 5.5.1 with a MVME5500 powerPc board. i have a question concerning the implementation of the DPIO2 pmc card on a mvme5500 powerPC. if i use the driver from vmetro i get the ...

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Thread: DPIO2 MVME 5500

  1. DPIO2 MVME 5500

    hello,
    we are using tornado 2.2.1 and vxWorks 5.5.1 with a MVME5500 powerPc
    board. i have a question concerning the implementation of the DPIO2 pmc
    card on a mvme5500 powerPC.
    if i use the driver from vmetro i get the following output:

    -> dpio2Configure(2,0x83000000);
    pBus 2, pDev 6, intPin 1
    value = 2146435072 = 0x7ff00000
    ->
    ->
    -> dpio2Start(1);

    DPIO2 Device Driver - Release: 2.4
    Copyright (C) 2001 - VMETRO, Inc. All rights reserved.
    Creation date: Feb 18 2004, 12:00:43

    dpio2Drv for use DPIO1 == 1 terminated with 0x7!
    devName:[/dpio2/2] at iPMCSlot: 2 numberSlots 2
    dpio2DevCreate for 2 Slot failed!
    dpio2DevCreate for 2 Slot OK!
    drv name
    0 /null
    1 /tyCo/0
    1 /tyCo/1
    4 FTTserver:
    6 /vio
    7 /dpio2/2
    found device at bus:2 with deviceNo:6 and FuncNo:0
    Selecting SYNC mode 0 disables EOT mode 2
    found dpioType 0x0!
    dpioGetDevNames: return noNames=0x1 dpioId=0x20
    fttL3DpioInit: FIFO size -1 and fifoAdr 0xffffffff! CMD 0x3f6 1014
    fttL3DpioInit: File descriptor is 6.
    value = 37 = 0x25 = '%'
    -> pciHeaderShow(2,6,0);
    vendor ID = 0x129a
    device ID = 0xdd11
    command register = 0x0006
    status register = 0x0200
    revision ID = 0x01
    class code = 0x11
    sub class code = 0x00
    programming interface = 0x00
    cache line = 0x00
    latency time = 0xff
    header type = 0x00
    BIST = 0x00
    base address 0 = 0x83000008
    base address 1 = 0x83800000
    base address 2 = 0x00000000
    base address 3 = 0x00000000
    base address 4 = 0x00000000
    base address 5 = 0x00000000
    cardBus CIS pointer = 0x00000000
    sub system vendor ID = 0x129a
    sub system ID = 0xdd11
    expansion ROM base address = 0x00000000
    interrupt line = 0x50
    interrupt pin = 0x01
    min Grant = 0x00
    max Latency = 0x00
    value = 0 = 0x0

    Device at bus 2, device 6 is a DPIO2-FB with FPGA code B0513

    my question is now: why cant the program read the fifo ? maybe iam
    doing something wrong in the pci mapping. can someone give me a hint on
    what i have to change and what not ? i implemented in the
    sysLib.c the following lines:
    {
    (void *) 0x83000000, /* Virtuall Address */
    (void *) 0x83000000, /* Physical Address (must be same as above)
    */
    0x02000000, /* 32 MB for 1st DPIO */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
    }

    so can anyone give me a hint what could be wrong

    thanks in advance
    andreas


  2. Re: DPIO2 MVME 5500

    On 2006-09-01, Andreas wrote:
    > -> pciHeaderShow(2,6,0);
    > base address 0 = 0x83000008
    > base address 1 = 0x83800000
    >
    > my question is now: why cant the program read the fifo ? maybe iam
    > doing something wrong in the pci mapping. can someone give me a hint on
    > what i have to change and what not ? i implemented in the
    > sysLib.c the following lines:
    > {
    > (void *) 0x83000000, /* Virtuall Address */
    > (void *) 0x83000000, /* Physical Address (must be same as above)
    > */


    I can't be certain, since I'm not using a DPIO, but on *my* MVME5500 the
    BSP is pretty insistent about mapping the Universe II VMEbus adapter to
    0x83000000.
    --
    roger ivie
    rivie@ridgenet.net

  3. Re: DPIO2 MVME 5500

    >
    > my question is now: why cant the program read the fifo ? maybe iam
    > doing something wrong in the pci mapping. can someone give me a hint on
    > what i have to change and what not ? i implemented in the
    > sysLib.c the following lines:
    > {
    > (void *) 0x83000000, /* Virtuall Address */
    > (void *) 0x83000000, /* Physical Address (must be same as above)
    > */
    > 0x02000000, /* 32 MB for 1st DPIO */
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE,
    > VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
    > }
    >


    You shouldn't have done this. The BSP already maps the PCI spaces.
    Probably not causing your problem, but wrong nonetheless.

    GV


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