mib2Tbl - VxWorks

This is a discussion on mib2Tbl - VxWorks ; Hello, Can someone please answer a few questions on vxWorks MIB2 implementation- -Which layer is responsible for poulating the the correct values in endObj->mib2Tbl ? -Specifically, where is the number of in & out octets and in & out packets ...

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Thread: mib2Tbl

  1. mib2Tbl

    Hello,
    Can someone please answer a few questions on vxWorks MIB2
    implementation-

    -Which layer is responsible for poulating the the correct values in
    endObj->mib2Tbl ?
    -Specifically, where is the number of in & out octets and in & out
    packets counted?
    -Are these normally read from the hardware registers or counted in the
    network (END) drivers?

    Thanks,
    LJ


  2. Re: mib2Tbl

    LJ wrote:
    > Hello,
    > Can someone please answer a few questions on vxWorks MIB2
    > implementation-
    >
    > -Which layer is responsible for poulating the the correct values in
    > endObj->mib2Tbl ?
    > -Specifically, where is the number of in & out octets and in & out
    > packets counted?
    > -Are these normally read from the hardware registers or counted in the
    > network (END) drivers?
    >
    > Thanks,
    > LJ


    The END layer is responsible for populating MIB2 counters. On
    lower-end chipsets, this is done purely with statistics code in the END
    driver. On better network cards (i.e. Intel Pro/1000) these are
    populated with hardware register values. However, even on these more
    feature-rich chipsets, the software may override the hardware registers
    by counting packets differently. For instance, a card may count a
    packet as "Too Long" if it exceeds 1518 bytes, but if you intend to
    accept 802.1Q tagged packets, a packet should only be marked "Too Long"
    if it exceeds 1522 bytes.

    Matt


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