about MPC8260 cache problem - VxWorks

This is a discussion on about MPC8260 cache problem - VxWorks ; hello,everyone. I do have a question about MPC8260 cache, first of all, I explain my system enviroment. 1. tornado2.0/vxworks 5.4 2. trace32 ICD 3. MPC 8260 processor card memory map 0x0000_0000------0x0200_0000, 60xbus SDRAM(32M) 0x2000_0000------0x0300_0000 local bus SDRAM(16M) MPC8260 Internal memory ...

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Thread: about MPC8260 cache problem

  1. about MPC8260 cache problem

    hello,everyone.

    I do have a question about MPC8260 cache, first of all, I explain my
    system enviroment.

    1. tornado2.0/vxworks 5.4
    2. trace32 ICD
    3. MPC 8260 processor card
    memory map
    0x0000_0000------0x0200_0000, 60xbus SDRAM(32M)
    0x2000_0000------0x0300_0000 local bus SDRAM(16M)
    MPC8260 Internal memory map 0x0f000_0000(base address, orignal
    0x0470_0000
    , after reset, I set to IMMR base to 0x0f00_0000)
    boot flash 0xffe0_0000-----0xffff_ffff

    my sysBatDesc[] and sysPhysMemDesc[] is as following:

    UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */
    ((0xFFe000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0xFFe000000&_MMU_LBAT_BRPN_MASK ) | _MMU_LBAT_PP_RONLY |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */
    ((0xFFF000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0xFFF000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RONLY |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 2 */
    ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 3 */
    ((0x0f000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0x0f000000& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 0 */
    ((0xFFe000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0xFFe000000&_MMU_LBAT_BRPN_MASK ) | _MMU_LBAT_PP_RONLY |
    _MMU_LBAT_CACHE_INHIBIT),


    /* D BAT 1 */
    ((0xFFF000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0xFFF000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RONLY |
    _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 2 */
    ((0& _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    _MMU_UBAT_VS| _MMU_UBAT_VP ),
    ((0& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 3 */
    ((0x0f000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K |
    _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((0x0f000000& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),
    };

    PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {

    #if 0 /*removed from this PTE table, move to BAT table */

    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID | VM_STATE_WRITABLE |
    VM_STATE_CACHEABLE_NOT
    },
    #endif
    {
    /* RAM on 60x bus - Must be second entry for Auto Sizing */

    (void *) 0x100000,
    (void *) 0x100000,
    0x020000000- 0x100000,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    #if 0 /*removed from this PTE table, move to BAT table */
    {
    /* MPC8260 Internal Memory Map */

    (void *) DEFAULT_IMM_ADRS,/*0x0f00_0000*/
    (void *) DEFAULT_IMM_ADRS,
    IMM_SIZE, /*128K*/
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID | VM_STATE_WRITABLE |
    VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },
    #endif
    {
    /* RAM on local bus - Must be second entry for Auto Sizing */

    (void *) LOCAL_SDRAM_START_ADDR,/*local sdram address
    0x02000_0000*/
    (void *) LOCAL_SDRAM_START_ADDR,
    LOCAL_BUS_SDRAM_SIZE, /*memory size 16M*/
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID | VM_STATE_WRITABLE |
    VM_STATE_CACHEABLE_NOT

    },
    #if 0 /*removed from this PTE table, move to BAT table */
    {
    /* Flash */

    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID | VM_STATE_WRITABLE |
    VM_STATE_CACHEABLE_NOT
    }
    #endif
    };

    when using config above, I only enable IMMU(disable DMMU), vxworks work
    fine,and I test its performance to only enabling I-CACHE and disable
    I-CACHE. I use it FOR loop to
    add a variable from 0 to 0x1000000,when disabling I- CACHE, it take 27
    second, when enabling I
    -CACHE, it take 12 second. Is the result normal or abnormal ?

    in addition, when I enable both IMMU and DMMU using config above,
    vxworks crash, and
    I use TRACE32 trace this source code, finding usrMmuInit()(in
    usrConfig.c) initialize MMU successfully, but excuting subsequent
    functions, vxwork crash.

    I also find that when I disable IMMU ,then enable DMMU,and set
    IBAT2[BL] to 256M

    vxwork may work ,but performance is very poor. meanwhile, when setting
    IBAT2[BL] to 4M ,I use trace32 trace it , vxworks crash when executing
    i iosInit().

    may anyone give me a help or explanantion to solve the problem?
    thank you for your help


  2. Re: about MPC8260 cache problem

    I don't know if it's the cause of your problem or not but the value
    0xFFe000000 for IBAT0 and DBAT0 seems to have one too many zeros.

    --


    Regards,


    Graham Baxter - AVAILABLE SOON FOR A NEW ASSIGNMENT
    Freelance Software Engineer (VxWorks, Linux and pSOS BSPs)
    Graham Baxter (Software) Limited
    http://www.gbsw.co.uk
    fromnewsgrp@NOSPAMgbsw.co.uk



    "linkdata40" wrote in message
    news:1136949083.200151.19360@g47g2000cwa.googlegro ups.com...
    > hello,everyone.
    >
    > I do have a question about MPC8260 cache, first of all, I explain my
    > system enviroment.
    >
    > 1. tornado2.0/vxworks 5.4
    > 2. trace32 ICD
    > 3. MPC 8260 processor card
    > memory map
    > 0x0000_0000------0x0200_0000, 60xbus SDRAM(32M)
    > 0x2000_0000------0x0300_0000 local bus SDRAM(16M)
    > MPC8260 Internal memory map 0x0f000_0000(base address, orignal
    > 0x0470_0000
    > , after reset, I set to IMMR base to 0x0f00_0000)
    > boot flash 0xffe0_0000-----0xffff_ffff
    >
    > my sysBatDesc[] and sysPhysMemDesc[] is as following:
    >
    > UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    > {
    > /* I BAT 0 */
    > ((0xFFe000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    > _MMU_UBAT_VS | _MMU_UBAT_VP),
    > ((0xFFe000000&_MMU_LBAT_BRPN_MASK ) | _MMU_LBAT_PP_RONLY |
    > _MMU_LBAT_CACHE_INHIBIT),
    >
    > /* I BAT 1 */
    > ((0xFFF000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    > _MMU_UBAT_VS | _MMU_UBAT_VP),
    > ((0xFFF000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RONLY |
    > _MMU_LBAT_CACHE_INHIBIT),
    >
    > /* I BAT 2 */
    > ((0 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    > _MMU_UBAT_VS | _MMU_UBAT_VP),
    > ((0 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    > _MMU_LBAT_CACHE_INHIBIT),
    >
    > /* I BAT 3 */
    > ((0x0f000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K |
    > _MMU_UBAT_VS | _MMU_UBAT_VP),
    > ((0x0f000000& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    > _MMU_LBAT_CACHE_INHIBIT),
    >
    > /* D BAT 0 */
    > ((0xFFe000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    > _MMU_UBAT_VS | _MMU_UBAT_VP),
    > ((0xFFe000000&_MMU_LBAT_BRPN_MASK ) | _MMU_LBAT_PP_RONLY |
    > _MMU_LBAT_CACHE_INHIBIT),
    >
    >
    > /* D BAT 1 */
    > ((0xFFF000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    > _MMU_UBAT_VS | _MMU_UBAT_VP),
    > ((0xFFF000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RONLY |
    > _MMU_LBAT_CACHE_INHIBIT),
    >
    > /* D BAT 2 */
    > ((0& _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M |
    > _MMU_UBAT_VS| _MMU_UBAT_VP ),
    > ((0& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    > _MMU_LBAT_CACHE_INHIBIT),
    >
    > /* D BAT 3 */
    > ((0x0f000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K |
    > _MMU_UBAT_VS | _MMU_UBAT_VP),
    > ((0x0f000000& _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    > _MMU_LBAT_CACHE_INHIBIT),
    > };
    >
    > PHYS_MEM_DESC sysPhysMemDesc [] =
    > {
    > {
    >
    > #if 0 /*removed from this PTE table, move to BAT table */
    >
    > /* Vector Table and Interrupt Stack */
    >
    > (void *) LOCAL_MEM_LOCAL_ADRS,
    > (void *) LOCAL_MEM_LOCAL_ADRS,
    > RAM_LOW_ADRS,
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE,
    > VM_STATE_VALID | VM_STATE_WRITABLE |
    > VM_STATE_CACHEABLE_NOT
    > },
    > #endif
    > {
    > /* RAM on 60x bus - Must be second entry for Auto Sizing */
    >
    > (void *) 0x100000,
    > (void *) 0x100000,
    > 0x020000000- 0x100000,
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE |
    > VM_STATE_MASK_MEM_COHERENCY,
    > VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE |
    > VM_STATE_MEM_COHERENCY
    > },
    >
    > #if 0 /*removed from this PTE table, move to BAT table */
    > {
    > /* MPC8260 Internal Memory Map */
    >
    > (void *) DEFAULT_IMM_ADRS,/*0x0f00_0000*/
    > (void *) DEFAULT_IMM_ADRS,
    > IMM_SIZE, /*128K*/
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE |
    > VM_STATE_MASK_GUARDED,
    > VM_STATE_VALID | VM_STATE_WRITABLE |
    > VM_STATE_CACHEABLE_NOT |
    > VM_STATE_GUARDED
    > },
    > #endif
    > {
    > /* RAM on local bus - Must be second entry for Auto Sizing */
    >
    > (void *) LOCAL_SDRAM_START_ADDR,/*local sdram address
    > 0x02000_0000*/
    > (void *) LOCAL_SDRAM_START_ADDR,
    > LOCAL_BUS_SDRAM_SIZE, /*memory size 16M*/
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE |
    > VM_STATE_MASK_MEM_COHERENCY,
    > VM_STATE_VALID | VM_STATE_WRITABLE |
    > VM_STATE_CACHEABLE_NOT
    >
    > },
    > #if 0 /*removed from this PTE table, move to BAT table */
    > {
    > /* Flash */
    >
    > (void *) ROM_BASE_ADRS,
    > (void *) ROM_BASE_ADRS,
    > ROM_SIZE,
    > VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |
    > VM_STATE_MASK_CACHEABLE,
    > VM_STATE_VALID | VM_STATE_WRITABLE |
    > VM_STATE_CACHEABLE_NOT
    > }
    > #endif
    > };
    >
    > when using config above, I only enable IMMU(disable DMMU), vxworks work
    > fine,and I test its performance to only enabling I-CACHE and disable
    > I-CACHE. I use it FOR loop to
    > add a variable from 0 to 0x1000000,when disabling I- CACHE, it take 27
    > second, when enabling I
    > -CACHE, it take 12 second. Is the result normal or abnormal ?
    >
    > in addition, when I enable both IMMU and DMMU using config above,
    > vxworks crash, and
    > I use TRACE32 trace this source code, finding usrMmuInit()(in
    > usrConfig.c) initialize MMU successfully, but excuting subsequent
    > functions, vxwork crash.
    >
    > I also find that when I disable IMMU ,then enable DMMU,and set
    > IBAT2[BL] to 256M
    >
    > vxwork may work ,but performance is very poor. meanwhile, when setting
    > IBAT2[BL] to 4M ,I use trace32 trace it , vxworks crash when executing
    > i iosInit().
    >
    > may anyone give me a help or explanantion to solve the problem?
    > thank you for your help
    >




  3. Re: about MPC8260 cache problem

    thank you for your reply.

    I am sorry to my error spelling, I check my source code, it is right,
    is 0xffe0_0000, can you give more information about this problem? it
    bother
    me for a week,

    thank you again


  4. Re: about MPC8260 cache problem

    [big snip about system crashing with data cache enabled]

    Are you sure that all of your I/O and especially Ethernet buffer
    memory is not cachable? There is a separate memory allocation
    routine for allocating non-cachable buffers.







  5. Re: about MPC8260 cache problem

    I see MotFccEnd.c, I make sure that the buffer for ethernet driver is
    in BD table(i.e. ,in DPRAM),and DPRAM have been marked as
    non-cacheable in BAT table, meanwhile, Tx/Rx buffer in my SCC1 for UART
    used for console was also in DPRAM.

    to the problem, today ,I see some info on web, maybe it is relevant to
    BCR[PLDP] setting. let me try it !


  6. Re: about MPC8260 cache problem

    Hi, I only have experience of VxWorks 5.5 and MPC8270, but I am
    assuming they are similar:

    1. If you are generating a bootrom, then the MMU code for vxWorks is
    not included. This means that the bootrom can run very slowly. You can
    increase the performance significantly by turning on the I-CACHE in
    romInit.s by using the following code fragment:

    #ifdef USER_I_CACHE_ENABLE

    /* Unlock, invalidate and enable the Instruction Cache. */
    lis r5,HIADJ(_PPC_HID0_ILOCK)
    addi r5,r5,LO(_PPC_HID0_ILOCK)
    andc r4,r4,r5
    mtspr HID0,r4
    isync
    lis r5,HIADJ(_PPC_HID0_ICE|_PPC_HID0_ICFI)
    addi r5,r5,LO(_PPC_HID0_ICE|_PPC_HID0_ICFI)
    or r4,r4,r5
    mtspr HID0,r4
    isync
    sync
    lis r5,HIADJ(_PPC_HID0_ICFI)
    addi r5,r5,LO(_PPC_HID0_ICFI)
    andc r4,r4,r5
    mtspr HID0,r4
    isync
    sync

    #endif USER_I_CACHE_ENABLE

    I put this code in just before the stack initialisation. This means
    that the code that clears the RAM runs in the cache, again, this
    significantly improves performance.

    2. You shouldn't really need to do any messing about with the cache
    enable bits. Defining USER_I_CACHE_ENABLE and USER_D_CACHE_ENABLE in
    config.h should do all the work for you. You MUST however make sure
    that your BAT array and your PTE array in sysLib.c are absolutely
    correct.....

    3. Make sure that none of the BAT regions overlap the PTE regions and
    that no two PTE regions overlap.

    4. Unused entries in the BAT table should be set to "0, 0".

    5. Remember that the IBAT's are only for use with code execution. You
    should only enable an IBAT for an area of memory where ONLY code will
    execute, for example the ROM, which can safely be I-cached. You do not
    need to set up an IBAT, for example, for the internal registers.

    6. Use the PTE table for RAM managed by VxWorks. Although the PTE will
    be large and consume memory, it means that the vxWorks functions for
    allocating non-cacheable memory will work. Do not use DBAT entries for
    main system RAM.

    7. Remember that an area defined for PTE's is used for both the I-cache
    and the D-cache.

    8. You can use DBAT entries for things like memory mapped hardware,
    Flash memory (for reprogramming) & RAM not managed by VxWorks.

    Specific to your tables above:
    a) You shouldn't cache inhibit IBAT0 & IBAT1
    b) IBAT2 & IBAT3 should not be defined, use 0,0 and 0,0 respectively
    c) DBAT0 & DBAT1 will actually need to be RW if you intend to use TFFS
    or program the Flash on the fly. You should also include the
    _MMU_LBAT_GUARDED bit.
    d) DBAT2; don't put the vector table in a DBAT, just use a PTE entry.
    Your size here is wrong anyway, it should only be 64K, not 1M. Set this
    to 0,0
    e) DBAT3 I would also add the _MMU_LBAT_GUARDED flag.
    f) Put the vector table back in as a PTE.

    I would also advise that you build in MotFcc2End.c into your BSP as
    this is the improved version of the driver for the PowerQUICC II. You
    can find this in one of the other ADS82xx directories in the "config"
    folder.

    Good luck,
    Andrew.


  7. Re: about MPC8260 cache problem

    thank your for your warm-heart. Item 3-8 is very important to me.

    to Item 1--2 , my boot time is less than 1 s, I had done it as you say
    similarly.

    anyway , thank you very much again. let me retry it tonight.


  8. Re: about MPC8260 cache problem

    Do you have a jtag interface so that you can see exactly what
    instruction your system is crashing on?

    Have you invalidated all the entries in the cache before
    enabling? I'm not sure if this problem occurs after a power-up,
    but I've seen pretty unusual behavior when data cache is enabled,
    disabled, and reenabled if the proper flushes/invalidates are not done.

    Remember that the stack gets cached as well. I also don't see
    where you set the cache mode to either write-back or write-through.
    Can't remember where this is done, but since I remember something
    about this and don't see anything in what you first posted, perhaps
    you are missing something.

    Who knows, I might actually have to go and look at our code
    to see what we do....


    "linkdata40" wrote in message
    news:1137113333.935290.303150@z14g2000cwz.googlegr oups.com...
    > thank your for your warm-heart. Item 3-8 is very important to me.
    >
    > to Item 1--2 , my boot time is less than 1 s, I had done it as you say
    > similarly.
    >
    > anyway , thank you very much again. let me retry it tonight.
    >




  9. Re: about MPC8260 cache problem

    when using trace32 ICD to trace source code, I found vxworks is on the
    fly after executing iosInit()(in usrConfig.c). before executing
    iosInit(), usrMmuInit() initialize MMU successfully, and
    HID0[ICE],[DCE] is set 1; sometime,I also found vxworks crash or
    restart when executing sysClkConnect() (the situation occur when I add
    cachePipeFlush() after cacheLibInit()) or iosInit(), hyperterminal will
    report "exteral interrupt level exception", and vxworks restart.

    I have ever add the function below(if error , please correct )after
    usrMmuInit(), but I found it do not constribute to do better than ever.
    when

    enabling I-Cache and D-Cache, vxwork always crash or restart. I suspect
    my SDRAM or DMMU.

    flushDataCache:

    li r6, 0x0 # r6 contains a block-aligned address in memory
    with which to fill
    # the data cache with.
    For this example, address 0x0 is used

    li r1, 0x200 # CTR = number of data blocks
    to load
    mtctr r1 # Number of blocks = (16K) / (32
    Bytes/block)
    # = 2^14 / 2^5 = 2^9 = 0x200

    mr r8, r1 # Save the total number of blocks in cache to

    # Load the entire cache with known data
    loop:
    lwz r2, 0(r6)
    addi r6, r6, 32 # Find the next block
    bdnz loop # Decrement the counter, and
    # branch if CTR != 0

    # Now, flush the cache with dcbf instructions
    li r6, 0x0 # Address of first block
    mtctr r8 # Number of blocks

    loop2:
    dcbf r0, r6
    addi r6, r6, 32 # Find the next block
    bdnz loop2 # Decrement the counter, and
    # branch if CTR != 0
    bclr 20,0

    invalDataCache:
    # Set and then clear the HID0[DCFI] bit, bit 21
    mfspr r1, HID0
    mr r2, r1
    ori r1, r1, 0x0400
    mtspr HID0, r1
    mtspr HID0, r2
    sync
    bclr 20,0


  10. Re: about MPC8260 cache problem

    Incidently, I am facing the same problem now. Were you able to find the root cause and fix it?

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