Newsgroups: comp.sys.powerpc.tech
From: mart...@bezeqint.net - Find messages by this author
Date: 6 Nov 2005 14:10:01 -0800
Local: Mon, Nov 7 2005 12:10 am
Subject: HID0 register initialization on G2 core (8270 processr)
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I am using the 8270 (PPC G2 core) with Vxworkd OS.


Originally I have taken the EST 8260 BSP and adapted it to the 8270
with G2 PPC core.


Within rominit.s (board initialization file) I am not sure if the
following lines that initialize the
HID0 register are written according the rules stated by the G2 core
manual:


mfspr r7,HID0 /* r7 = HID0 */
andi. r7,r7,0xcfff /* make sure lock bits are
clear */
/* r8 has ICE,DCE,ICI,DCI bits
set */
ori r8,r7,(_PPC_HID0_ICE | _PPC_HID0_DCE | _PPC_HID0_ICFI |

_PPC_HID0_DCFI)
andi. r7,r7,0x03ff /* r7 has enable bits cleared
*/
sync
mtspr HID0,r8 /* HIDO = r8 */
isync
sync
mtspr HID0,r7 /* HIDO = r7 */
isync


According to te G2 core the invalidation of D-cache / I-cache is
achieved by setting and clearing the DCFI/ICFI bit in two consecutive
mtspr [ HID0 ] operations. This rule is not followed by the above code.

Question 1: How critical is it not following the "two consecutive HID0

operations" rule ?


Question 2: Should the G2 core D-cache/I-cache be enabled during cache

invalidation ?


Question 3:
Isn't this code too complex ? It does to much in several lines:
A. unlocks the I-cache and D-cache
B. Invalidates the I-cache and D-cache
C. Disables the I-cache and D-cache
D. Disables parity, DPM, and low power modes


Is this legal at all ?
Wouldn't it be more correct to write separate code for each
functionality of 1-4 above.


Thanks,
Martin Roth