Background: Inside Intel's Tera-scale project - VMS

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  1. Background: Inside Intel's Tera-scale project

    Background: Inside Intel's Tera-scale project

    Santa Clara (CA) - Last week, Intel released eight technical papers
    providing details about its Tera-scale project. TG Daily had an
    opportunity to discuss the technology with Jerry Bautista, director of
    technology management at Intel. Could Tera-scale become the x86
    killer?

    The Tera-scale project is currently has over 100 separate teams work
    on it. Intel is working on everything from electrical foundations all
    the way up to the software. Some of the research Bautista was able to
    share with us indicated how powerful this project is and why Intel is
    throwing so many resources at it.

    In February 2007, a prototype chip was built on 65nm process
    technologies. It clocked at nearly 3.16 - 5.8 GHz, had 80 separate
    compute cores operating internally, and it ran through six different
    customized benchmarks with each using traditional compute burdens.
    The result was a remarkable 1.01 Teraflops of parallel computing on
    just 62 watts of input power (1.63 Teraflops at 5.1 GHz and 175 watts,
    and 1.81 Teraflops at 5.7 GHz and 265 watts). While that level of
    computing for a single chip is impressive in and of itself, the
    process and mechanics of how Intel got there are at least as
    impressive.

    Click here to read the whole article:
    http://www.tgdaily.com/content/view/33657/135/

    NSR


  2. Re: Background: Inside Intel's Tera-scale project

    In article <1188990158.935070.195240@r29g2000hsg.googlegroups. com>,
    Neil Rieck writes:
    > Background: Inside Intel's Tera-scale project
    >
    > Santa Clara (CA) - Last week, Intel released eight technical papers
    > providing details about its Tera-scale project. TG Daily had an
    > opportunity to discuss the technology with Jerry Bautista, director of
    > technology management at Intel. Could Tera-scale become the x86
    > killer?
    >


    If this is going to be "the x86 killer" what do you suppose it will do
    to Itanium? :-)

    bill

    --
    Bill Gunshannon | de-moc-ra-cy (di mok' ra see) n. Three wolves
    bill@cs.scranton.edu | and a sheep voting on what's for dinner.
    University of Scranton |
    Scranton, Pennsylvania | #include

  3. Re: Background: Inside Intel's Tera-scale project

    Bill Gunshannon wrote:
    > In article <1188990158.935070.195240@r29g2000hsg.googlegroups. com>,
    > Neil Rieck writes:
    >
    >>Background: Inside Intel's Tera-scale project
    >>
    >>Santa Clara (CA) - Last week, Intel released eight technical papers
    >>providing details about its Tera-scale project. TG Daily had an
    >>opportunity to discuss the technology with Jerry Bautista, director of
    >>technology management at Intel. Could Tera-scale become the x86
    >>killer?
    >>

    >
    >
    > If this is going to be "the x86 killer" what do you suppose it will do
    > to Itanium? :-)



    What could it do to Itanic that it's owners/developers have not already
    done to Itanic?


  4. Re: Background: Inside Intel's Tera-scale project


    Neil Rieck wrote:
    > Background: Inside Intel's Tera-scale project
    >
    > Santa Clara (CA) - Last week, Intel released eight technical papers
    > providing details about its Tera-scale project. TG Daily had an
    > opportunity to discuss the technology with Jerry Bautista, director of
    > technology management at Intel. Could Tera-scale become the x86
    > killer?
    >
    > The Tera-scale project is currently has over 100 separate teams work
    > on it. Intel is working on everything from electrical foundations all
    > the way up to the software. Some of the research Bautista was able to
    > share with us indicated how powerful this project is and why Intel is
    > throwing so many resources at it.
    >
    > In February 2007, a prototype chip was built on 65nm process
    > technologies. It clocked at nearly 3.16 - 5.8 GHz, had 80 separate
    > compute cores operating internally, and it ran through six different
    > customized benchmarks with each using traditional compute burdens.
    > The result was a remarkable 1.01 Teraflops of parallel computing on
    > just 62 watts of input power (1.63 Teraflops at 5.1 GHz and 175 watts,
    > and 1.81 Teraflops at 5.7 GHz and 265 watts). While that level of
    > computing for a single chip is impressive in and of itself, the
    > process and mechanics of how Intel got there are at least as
    > impressive.
    >
    > Click here to read the whole article:
    > http://www.tgdaily.com/content/view/33657/135/
    >


    Apparently the editor who wrote the "x86 killer" lead-in for this
    article didn't take the time to read it. Or, Rick C. Hodgin didn't
    understand what he was writing. The Tera-scale project has nothing to
    do with instruction sets.

    ++
    "Even IA-32 cores could be integrated into the Tera-scale chip. An
    implementation of the Exoskeleton solution that Intel has been working
    on for IA-32 would allow the non-IA-32 cores to be presented to
    external software as if they were IA-32. This virtualization of
    compute resources opens up another door for the future."
    ++



  5. Re: Background: Inside Intel's Tera-scale project

    >Could Tera-scale become the x86 killer?

    My take on this is that this is like the IBM Blue-Gene project. Let some
    engineers play out there in the wold and come up with interesting
    technologies. Make a big demo of it, and then integrate some of those
    technologies into your commercial products.

    The 8086 instruction set is here to stay. How they implement its
    underpinning will likely change and it has already changed a lot since
    the original days of the 8086.

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