Intel's 6-core processor codenamed "Dunnington" ... - VMS

This is a discussion on Intel's 6-core processor codenamed "Dunnington" ... - VMS ; http://www.ddj.com/hpc-high-performa...ting/206904629 Intel has made public details about its upcoming multi-processor servers that are based on Intel's 6-core processor codenamed "Dunnington" and its new Itanium processor codenamed "Tukwila," along with disclosing technical features of its previously announced "Nehalem" and "Larrabee" processors. ...

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  1. Intel's 6-core processor codenamed "Dunnington" ...

    http://www.ddj.com/hpc-high-performa...ting/206904629

    Intel has made public details about its upcoming multi-processor
    servers that are based on Intel's 6-core processor codenamed
    "Dunnington" and its new Itanium processor codenamed "Tukwila," along
    with disclosing technical features of its previously announced
    "Nehalem" and "Larrabee" processors.

    Neil Rieck
    Kitchener/Waterloo/Cambridge,
    Ontario, Canada.
    http://www3.sympatico.ca/n.rieck/


  2. Re: Intel's 6-core processor codenamed "Dunnington" ...

    Neil Rieck wrote:

    > "Dunnington" and its new Itanium processor codenamed "Tukwila," along
    > with disclosing technical features of its previously announced
    > "Nehalem" and "Larrabee" processors.



    More importantly, the introduction of the common system interconnect (or
    whatevre its name is this week). Carly, back in january 2004, had
    announced the CSI for both the 8086 and that IA64 contraption for 2007.
    So it is a bit late.

    But the 8086 will now gain enterprise class system architecture.

  3. Re: Intel's 6-core processor codenamed "Dunnington" ...


    "JF Mezei" wrote in message
    news:47e3220c$0$28115$c3e8da3@news.astraweb.com...
    > Neil Rieck wrote:
    >
    > > "Dunnington" and its new Itanium processor codenamed "Tukwila," along
    > > with disclosing technical features of its previously announced
    > > "Nehalem" and "Larrabee" processors.

    >
    >
    > More importantly, the introduction of the common system interconnect (or
    > whatevre its name is this week). Carly, back in january 2004, had
    > announced the CSI for both the 8086 and that IA64 contraption for 2007.
    > So it is a bit late.
    >
    > But the 8086 will now gain enterprise class system architecture.


    The "8086" has had architecture which plenty of enterprises have been
    relying on for a while now, though there are also a couple of credible
    alternatives.

    Earlier this week HP announced its first 8-socket server since 2005, the
    Proliant DL785 G5, a 32-core (eight socket) 256GB (64 slot, so 512GB when
    8GB DIMMs arrive) 7U server with 11 PCIe slots, starting at $17K (according
    to http://www.theregister.co.uk/2008/03/17/hp_dl785/). HP's own info at
    http://h18004.www1.hp.com/products/s...5g5/index.html. This
    one isn't based on CSI, it's Opteron-based (so unlike CPQ/HP's Xeon 8-socket
    offerings using expensive-to-build custom non-Intel (Corollary?) chipsets,
    no custom chipset is needed).

    Just Windows or Linux (or Solaris/x86???) though? Even with VMware, is there
    much point, isn't something missing?



  4. Re: Intel's 6-core processor codenamed "Dunnington" ...

    On Mar 20, 7:41*pm, Neil Rieck wrote:
    >
    > http://www.ddj.com/hpc-high-performa...ting/206904629
    >

    Intel's pre-IDF briefing today offered a significant look at the chip
    giant's roadmap for 2008-2009, as well as some specific information on
    upcoming products that the company has previously kept quiet. Tukwila,
    Larrabee, Dunnington, and Nehalem were all topics of conversation as
    Intel laid out its 2008 strategy.

    http://arstechnica.com/news.ars/post...ming-cpus.html

    Neil Rieck
    Kitchener/Waterloo/Cambridge,
    Ontario, Canada.
    http://www3.sympatico.ca/n.rieck/


  5. Re: Intel's 6-core processor codenamed "Dunnington" ...

    On Mar 20, 10:48*pm, JF Mezei wrote:
    > Neil Rieck wrote:


    >
    > More importantly, the introduction of the common system interconnect (or
    > whatevre its name is this week). Carly, back in january 2004, had
    > announced the CSI for both the 8086 and that IA64 contraption for 2007.
    > So it is a bit late.
    >
    > But the 8086 will now gain enterprise class system architecture.


    I read somewhere that Intel might be better at marketing than
    designing CPUs. For example, lots of Intel literature talks about
    Pentium-4 being a RISC processor but we all know that those SIMD
    instructions (MMX/SSE, SSE2, SSE3, SSE4, etc.) are CISC. When asked
    about this at a technical simposium, Intel's response was something
    like "Pentium-4 is RISC when you only only use the RISC instruction
    set". OK this makes sense to me. Intel's CPU is whatever the user
    wants it to be.

    Likewise, calling Pentium (and chips after it) "8086" is like saying
    VAX-11 is really a PDP becuase VAX-11 could run most PDP code even
    though it could do many more things. The correct label for these Intel
    chips is "x86-64".

    Neil Rieck
    Kitchener/Waterloo/Cambridge,
    Ontario, Canada.
    http://www3.sympatico.ca/n.rieck/

  6. Re: Intel's 6-core processor codenamed "Dunnington" ...

    JF Mezei wrote:
    >
    > Neil Rieck wrote:
    >
    > > "Dunnington" and its new Itanium processor codenamed "Tukwila," along
    > > with disclosing technical features of its previously announced
    > > "Nehalem" and "Larrabee" processors.

    >
    > More importantly, the introduction of the common system interconnect (or
    > whatevre its name is this week). Carly, back in january 2004, had
    > announced the CSI for both the 8086 and that IA64 contraption for 2007.
    > So it is a bit late.
    >
    > But the 8086 will now gain enterprise class system architecture.


    Pretty amazing for an 8/16-bit processor in today's 64-bit age, eh? ;-)

    David J Dachtera
    (formerly dba) DJE Systems

  7. Re: Intel's 6-core processor codenamed "Dunnington" ...

    In article <47E3E5EE.164EA310@spam.comcast.net>, David J Dachtera writes:
    > JF Mezei wrote:
    >>
    >> Neil Rieck wrote:
    >>
    >> > "Dunnington" and its new Itanium processor codenamed "Tukwila," along
    >> > with disclosing technical features of its previously announced
    >> > "Nehalem" and "Larrabee" processors.

    >>
    >> More importantly, the introduction of the common system interconnect (or
    >> whatevre its name is this week). Carly, back in january 2004, had
    >> announced the CSI for both the 8086 and that IA64 contraption for 2007.
    >> So it is a bit late.
    >>
    >> But the 8086 will now gain enterprise class system architecture.

    >
    > Pretty amazing for an 8/16-bit processor in today's 64-bit age, eh? ;-)
    >


    Especially since the majority of its use is running a two-bit OS. ;^)

  8. Re: Intel's 6-core processor codenamed "Dunnington" ...

    On Mar 21, 7:53*pm, kuhrt.nospa...@encompasserve.org (Marty Kuhrt)
    wrote:
    > In article <47E3E5EE.164EA...@spam.comcast.net>, David J Dachtera writes:
    >

    [...snip...]
    >
    > Especially since the majority of its use is running a two-bit OS. *;^)
    >


    I have no doubt that OpenVMS is the best OS on the planet but I think
    it is wise to recall that the Rabbit once thought it could sleep while
    the Tortoise plodded on to win the race. OpenVMS on Itanium/Alpha/VAX
    appears to me to be sleeping while UNIX (in its many forms including
    Apple's Macintosh latest OS which is related to BSD) slowly crawl onto
    these new hex-cores.

    I'm sure many here will point out that OpenVMS helped pave the way for
    large SMP implementations which resulted in cool Alpha technology like
    Wildfire and Marvel. I couldn't agree more but need to remind people
    that these machines were very expensive and based upon CPU sockets.
    Remove the sockets and the price drops dramatically even though you've
    increased the core (CPU) count.

    There was once a time when the head of IBM thought the world would
    need only 10 super computers. There was once a time when the head of
    DEC didn't think common people needed personal computers. There was
    once a time when the head of Microsoft thought that 640k should be
    enough memory for anybody. Only Isaac Asimov pictured A.I. computers
    and robots living with us in our homes and offices. It is my belief
    that the equivalent of Asimov's "postronic brain" will be implemented
    in a manner closer to our human brain with integrated processors and
    memory devices. Software development in this area will increase as
    hardware becomes more powerful while at the same time becoming less
    expensive.

    I was recently reading some MMX release notes from 1997 and discovered
    that Pentium-3 chips were sold for $575 in quantities of 1000. Last
    month I purchased a new computer tower based upon Intel's Quad-core
    Q6600 with 2 GB of memory for $599 so I think you all can see where
    I'm going here. If OpenVMS never makes it onto these new ubiquitous
    hardware platforms, it will become relegated to the museum shelf right
    beside the buggy-whip display. (And HP will have lost another cash
    cow)

    Neil Rieck
    Kitchener/Waterloo/Cambridge,
    Ontario, Canada.
    http://www3.sympatico.ca/n.rieck/

  9. Re: Intel's 6-core processor codenamed "Dunnington" ...

    "Neil Rieck" wrote in message
    news:6f4afc99-00e5-4640-ad67-9c449a2d414b@n58g2000hsf.googlegroups.com...
    On Mar 20, 10:48 pm, JF Mezei wrote:
    > Neil Rieck wrote:


    >
    > More importantly, the introduction of the common system interconnect (or
    > whatevre its name is this week). Carly, back in january 2004, had
    > announced the CSI for both the 8086 and that IA64 contraption for 2007.
    > So it is a bit late.
    >
    > But the 8086 will now gain enterprise class system architecture.


    I read somewhere that Intel might be better at marketing than
    designing CPUs. For example, lots of Intel literature talks about
    Pentium-4 being a RISC processor but we all know that those SIMD
    instructions (MMX/SSE, SSE2, SSE3, SSE4, etc.) are CISC. When asked
    about this at a technical simposium, Intel's response was something
    like "Pentium-4 is RISC when you only only use the RISC instruction
    set". OK this makes sense to me. Intel's CPU is whatever the user
    wants it to be.

    =========
    Then first stage of the Intel & AMD processors is to convert the CISC
    instructions into a series of RISC instructions. CISC instructions are
    simply an abstraction at this point. Internally, chip manufacturers have
    implemented microcode to handle their CISC instruction sets simply because
    of the technical benefits they receive by using RISC. Externally, there is
    a huge legacy of binary files that they are continue to support, all of
    which use CISC instructions descended from the 8086 processor. There are
    also other benefits to using CISC instructions externally, one of which is
    smaller binaries for the same code.

    Mike.



  10. Re: Intel's 6-core processor codenamed "Dunnington" ...

    On Mar 22, 11:13*am, "Michael D. Ober"
    wrote:
    > "Neil Rieck" wrote in message
    >

    [...snip...]
    >
    > I read somewhere that Intel might be better at marketing than
    > designing CPUs. For example, lots of Intel literature talks about
    > Pentium-4 being a RISC processor but we all know that those SIMD
    > instructions (MMX/SSE, SSE2, SSE3, SSE4, etc.) are CISC. When asked
    > about this at a technical simposium, Intel's response was something
    > like "Pentium-4 is RISC when you only only use the RISC instruction
    > set". OK this makes sense to me. Intel's CPU is whatever the user
    > wants it to be.
    >
    > =========
    > Then first stage of the Intel & AMD processors is to convert the CISC
    > instructions into a series of RISC instructions. *CISC instructions are
    > simply an abstraction at this point. *Internally, chip manufacturers have
    > implemented microcode to handle their CISC instruction sets simply because
    > of the technical benefits they receive by using RISC. *Externally, thereis
    > a huge legacy of binary files that they are continue to support, all of
    > which use CISC instructions descended from the 8086 processor. *There are
    > also other benefits to using CISC instructions externally, one of which is
    > smaller binaries for the same code.
    >
    > Mike.


    You are 100% correct and I support the idea of being able to support
    old code bases. But MMX + SSE instructions are CISC instructions so,
    technically, Intel is being a little crafty when they say that Pentium
    is RISC.

    But in the end who really cares? Intel now has dual, quad, and hex
    cores capable of running RISC or CISC, so the majority of them could
    be running RISC programs while one (or more) of them could be locked
    into long SIMD instructions. Why is this important? Now these x86-64
    systems can do something the current generation of larger servers
    can't (at least not without installing specialized DSP hardware).

    Neil Rieck
    Kitchener/Waterloo/Cambridge,
    Ontario, Canada.
    http://www3.sympatico.ca/n.rieck/

  11. Re: Intel's 6-core processor codenamed "Dunnington" ...

    "Neil Rieck" wrote in message
    news:43ca498d-04d6-4f1d-8376-24647b171c8f@m36g2000hse.googlegroups.com...
    On Mar 22, 11:13 am, "Michael D. Ober"
    wrote:
    > "Neil Rieck" wrote in message
    >

    [...snip...]
    >
    > I read somewhere that Intel might be better at marketing than
    > designing CPUs. For example, lots of Intel literature talks about
    > Pentium-4 being a RISC processor but we all know that those SIMD
    > instructions (MMX/SSE, SSE2, SSE3, SSE4, etc.) are CISC. When asked
    > about this at a technical simposium, Intel's response was something
    > like "Pentium-4 is RISC when you only only use the RISC instruction
    > set". OK this makes sense to me. Intel's CPU is whatever the user
    > wants it to be.
    >
    > =========
    > Then first stage of the Intel & AMD processors is to convert the CISC
    > instructions into a series of RISC instructions. CISC instructions are
    > simply an abstraction at this point. Internally, chip manufacturers have
    > implemented microcode to handle their CISC instruction sets simply because
    > of the technical benefits they receive by using RISC. Externally, there is
    > a huge legacy of binary files that they are continue to support, all of
    > which use CISC instructions descended from the 8086 processor. There are
    > also other benefits to using CISC instructions externally, one of which is
    > smaller binaries for the same code.
    >
    > Mike.


    You are 100% correct and I support the idea of being able to support
    old code bases. But MMX + SSE instructions are CISC instructions so,
    technically, Intel is being a little crafty when they say that Pentium
    is RISC.

    But in the end who really cares? Intel now has dual, quad, and hex
    cores capable of running RISC or CISC, so the majority of them could
    be running RISC programs while one (or more) of them could be locked
    into long SIMD instructions. Why is this important? Now these x86-64
    systems can do something the current generation of larger servers
    can't (at least not without installing specialized DSP hardware).

    Neil Rieck
    Kitchener/Waterloo/Cambridge,
    Ontario, Canada.
    http://www3.sympatico.ca/n.rieck/


    Neil,

    You are absolutely correct in your assertion that it really no longer
    matters whether the underlying architecture is CISC or RISC. It appears the
    "religious" battle between the two was won by the consumer with vastly more
    powerful hardware.

    Mike.



  12. Re: Intel's 6-core processor codenamed "Dunnington" ...

    Neil Rieck wrote:

    > You are 100% correct and I support the idea of being able to support
    > old code bases. But MMX + SSE instructions are CISC instructions so,
    > technically, Intel is being a little crafty when they say that Pentium
    > is RISC.


    Does anyone care ? People see Intel/AMD cranking out new 8086s every
    couple of years with significant performance increases each time, and
    competition/volume driving prices down.

    Carly, for all her faults, was right in predicting that commodity
    "industry standard" would (to use Compaq's terminology) "eviscerate the
    underbelly of proprietary/low volume enterprise computing".

    In order to give the 8086 some real performance, Intel decided to build
    a tramnslator into risc instructions. So it may be correct to state that
    the actual CPU is RISC and is fronted by a CISC->RISC translator that
    still allows Intel to add fancy complex instructions to the 8086
    instruction set.

    And in the end, I think it may end up being an interesting way of
    gaining performance since, instead of some compiler generating a
    gazillion RISC instructions, you have one fancy instruction that is
    loaded from memory once and then decoded at CPU speed into optimised
    operations at a risc level inside the chip.

    This also yields to smaller memory footprint for executables, so a CPU's
    cache becomes more efficient.



  13. Re: Intel's 6-core processor codenamed "Dunnington" ...

    On Mar 22, 5:58*pm, JF Mezei wrote:
    > Neil Rieck wrote:
    > > You are 100% correct and I support the idea of being able to support
    > > old code bases. But MMX + SSE instructions are CISC instructions so,
    > > technically, Intel is being a little crafty when they say that Pentium
    > > is RISC.

    >
    > Does anyone care ? People see Intel/AMD cranking out new 8086s every
    > couple of years with significant performance increases each time, and
    > competition/volume driving prices down.
    >
    > Carly, for all her faults, was right in predicting that commodity
    > "industry standard" would (to use Compaq's terminology) "eviscerate the
    > underbelly of proprietary/low volume enterprise computing".
    >
    > In order to give the 8086 some real performance, Intel decided to build
    > a tramnslator into risc instructions. So it may be correct to state that
    > the actual CPU is RISC and is fronted by a CISC->RISC translator that
    > still allows Intel to add fancy complex instructions to the 8086
    > instruction set.
    >
    > And in the end, I think it may end up being an interesting way of
    > gaining performance since, instead of some compiler generating a
    > gazillion RISC instructions, you have one fancy instruction that is
    > loaded from memory once and then decoded at CPU speed into optimised
    > operations at a risc level inside the chip.
    >
    > This also yields to smaller memory footprint for executables, so a CPU's
    > cache becomes more efficient.
    >


    Yep. I don't want to start painting with a wide brush BUT having those
    MMX/SSE instructions there for occasional use is a good thing. Servers
    and word processors don't need them but then you need to ask the big
    question "what does Itanium bring to the table that wasn't already
    there with Alpha?"

    On an MMX/SSE related note: I saw a few good technology articles over
    at the folding-at-home news site which hint at where the industry in
    general might be in 10 years. Basically, after you adjust for CPU
    instruction rates, a fixed amount of science takes about two weeks on
    a CPU with no MMX/SSE instructions (no DSP instructions; BTW, this
    doesn't mean you couldn't add a DSP chipset when required). Add MMX/
    SSE and the same science is done 14x faster. Drop in an older ATI
    graphics card like the Radeon x1950, and the science is now done 70x
    faster by employing the ATI card's 48 stream processors. ATI is
    predicting that every computer in the future will contain embedded
    stream processors. Silicon is cheap so why not? (BTW, Intel's Core2
    technology powers down unused sections of the chip on-the-fly to save
    power so why not add stream processors then leave them powered off
    until needed?)

    http://ati.amd.com/technology/stream...ing/index.html
    http://ati.amd.com/technology/stream...g/folding.html

    Neil Rieck
    Kitchener/Waterloo/Cambridge,
    Ontario, Canada.
    http://www3.sympatico.ca/n.rieck/

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