PDP-11/45 dual Unibus

I think I've asked this before but didn't get a usable answer:

Does anyone understand how the dual Unibi on PDP-11/45s work? I've heard of
people connecting pairs of PDP-11/45s together, and Figure 1-3 of EK-11045-MM
(on bitsavers) shows that you can unjumper the two Unibus channels from
each other leaving Unibus B attached to the "DUAL INPUT MEMORY CONTROL(S)"
but it's not at all clear what that means (it doesn't show where the other
channel hooks up). Would that mean UB A is for the I/O page only and UB
B is for DMA? (That wouldn't work.) And if memory is shared, does that
mean all the memory has to live on one machine, or is there a way to decide
which memory lives where?

As you can imagine my goal is to emulate these things in E11. I've tweaked
the mods for the PDP-11/74 mP emulation so that now (i.e. in the next
release, RSN) the multiple CPUs have the option of each having their own
private main memory, so effectively you can have up to 4 completely separate
PDP-11 systems, so I've been running RSTS and RT-11 simultaneously on an
AMD64 X2 DOS machine -- it's hilarious! The point would be to have the
various CPUs connected by the right kinds of IPLs though.

But I don't think totally separate memory is right. I have a hand-drawn
diagram of a dual 11/45 system used on a flight simulator (I think these
things have all been ported now but that's not the point) and it looks as
if one CPU has its Unibusses unjumpered and has all its own peripherals
(including disks) on one bus while the other one just runs straight into the
far end of the other CPU's jumpered Unibusses (after all its peripherals,
instead of a terminator). And there appears to be a mixture of Unibus
memory on both, and system memory (FASTbus I guess?) on the first CPU
(but apparently not the second).

I was expecting to have to emulate the DA11F Unibus window, which would
still be fun (so I'll do that too) but doesn't seem to be the answer here.
So is there something like the PDP-11/70 "Unibus fence" setting which decides
which Unibus addresses the CPU's memory system (or Unibus map in the case of
the 11/70) responds to, and which are left for Unibus memory or nothing?
And how do NPRs work from the local Unibus to/from the shared one? Crazy...

Anyway if anyone remembers this stuff I'd love to hear about it please.
I have a dim recollection that some low-end model (11/05?) had a jumper to
make it not be the bus arbitrator (so it used NPRs to talk to the Unibus),
and one of the MicroVAXes (KA630?) had something similar, but this seems
quite a bit more complicated.

John Wilson
D Bit

On Mar 9, 12:16*am, John Wilson <wil...@dbit.com> wrote:[color=blue]
> I think I've asked this before but didn't get a usable answer:[/color]

I asked it before, back in 1996, probably inspired by the same
processor handbooks you are looking at now, and am not sure I got a
usable answer either :-).

But in 2001, John Holden mentioned the following, maybe it helps
answer the question of where these were used:

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From: John Holden <jo...@psychwarp.psych.usyd.edu.au>
Newsgroups: vmsnet.pdp-11
Subject: Re: multiprocessor 11/45
Date: Thu, 15 Mar 2001 08:07:36 +1100
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Tom Uban wrote:[color=blue]
>
> The 11/45 processor handbook talks about the utility of a multiprocessor
> system, considering the dual UNIBUS architecture and fast/slow memory
> scheme.
>
> I know that many discussions have gone by about a multiprocessor 11/70,
> but did DEC ever make (internally?), produce, or sell a multiprocessor
> 11/45 system?
>
> Did anyone in put a pair (or more) of 11/45's together on their own?[/color]

I had an 11/45 with a 11/20 front end, but it gets tricky. You can
only
separate the two Unibuses (unbusi?) if you have fastbus memory. The
controllers were dual ported, one to unibus B and the other a direct
path to the processor. Unibus A was always used by the processor, and
had the bus arbitration logic. Unibus B had no such logic, and was
used
for DMA transfers from peripherals to the fastbus memory.

If you separate the buses (just remove a jumper), and run a second
processor on Unibus B there is a problem. The second processor and
its peripherals have full access to the fastbus memory (only), but the
peripherals on the 11/45 had no access.

In my case using an 11/20 (which doesn't have memory management) the
fastbus memory has to be strapped into the first 56Kb of memory. The
DMA
devices on the 11/45 couldn't have access to this memory, so I had to
write a special bootstrap loader that buffered data in normal memory,
then transferred it to the fastbus segment.

A different hardware solution was the 'Unibus Window', where you could
transparently map chunks of memory (or peripherals) between to
unibus machines.

The dual Unibus is all about the max two sections of Fastbus Memory that are optional in 11/45, /50 and /55. This memory is dual ported: CPU gets access through the Fastbus, peripherals get DMA access through the Unibus when the B-bus is interconnected with the A-bus on the machine.

When splitting this A+B bus and connecting B into another PDP-11, you get shared memory. The second machine accesses the Fastbus memory via the Unibus and the local machine via the Fastbus. Restrictions: no DMA to this section of memory on the local machine. (also no access to parity registers on the local machine to mention a detail overlooked by DEC)

Application: dual processors in Link Miles flight simulator for DC-10. Used 11/45 type for the one that shares the memory to an 11/44 connected to the B-bus. This 11/45 does the number crunching, the 11/44 the I/O