Re: PDP-11/45 dual Unibus
On Mar 9, 12:16*am, John Wilson <wil...@dbit.com> wrote:[color=blue]
> I think I've asked this before but didn't get a usable answer:[/color]
I asked it before, back in 1996, probably inspired by the same
processor handbooks you are looking at now, and am not sure I got a
usable answer either :-).
But in 2001, John Holden mentioned the following, maybe it helps
answer the question of where these were used:
From: John Holden <jo...@psychwarp.psych.usyd.edu.au>
Subject: Re: multiprocessor 11/45
Date: Thu, 15 Mar 2001 08:07:36 +1100
Organization: University of Sydney, Australia
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Tom Uban wrote:[color=blue]
> The 11/45 processor handbook talks about the utility of a multiprocessor
> system, considering the dual UNIBUS architecture and fast/slow memory
> I know that many discussions have gone by about a multiprocessor 11/70,
> but did DEC ever make (internally?), produce, or sell a multiprocessor
> 11/45 system?
> Did anyone in put a pair (or more) of 11/45's together on their own?[/color]
I had an 11/45 with a 11/20 front end, but it gets tricky. You can
separate the two Unibuses (unbusi?) if you have fastbus memory. The
controllers were dual ported, one to unibus B and the other a direct
path to the processor. Unibus A was always used by the processor, and
had the bus arbitration logic. Unibus B had no such logic, and was
for DMA transfers from peripherals to the fastbus memory.
If you separate the buses (just remove a jumper), and run a second
processor on Unibus B there is a problem. The second processor and
its peripherals have full access to the fastbus memory (only), but the
peripherals on the 11/45 had no access.
In my case using an 11/20 (which doesn't have memory management) the
fastbus memory has to be strapped into the first 56Kb of memory. The
devices on the 11/45 couldn't have access to this memory, so I had to
write a special bootstrap loader that buffered data in normal memory,
then transferred it to the fastbus segment.
A different hardware solution was the 'Unibus Window', where you could
transparently map chunks of memory (or peripherals) between to
Re: PDP-11/45 dual Unibus
The dual Unibus is all about the max two sections of Fastbus Memory that are optional in 11/45, /50 and /55. This memory is dual ported: CPU gets access through the Fastbus, peripherals get DMA access through the Unibus when the B-bus is interconnected with the A-bus on the machine.
When splitting this A+B bus and connecting B into another PDP-11, you get shared memory. The second machine accesses the Fastbus memory via the Unibus and the local machine via the Fastbus. Restrictions: no DMA to this section of memory on the local machine. (also no access to parity registers on the local machine to mention a detail overlooked by DEC)
Application: dual processors in Link Miles flight simulator for DC-10. Used 11/45 type for the one that shares the memory to an 11/44 connected to the B-bus. This 11/45 does the number crunching, the 11/44 the I/O