Vol 72 Issue 2 2004-02-09 Article 12308 from section "News"

Binary Compatibility and More

The dual-thread UltraSPARC[R] IV processor marks the first milestone in
Sun's Chip Multithreading (CMT) roadmap. Key highlights are:

- It provides up to two times the application throughput of the
UltraSPARC[R] III processor

- Binary compatibility with previous generations of SPARC[R]

- On-chip tags for 16 MBs of off-chip level 2 cache (8 MB per

- On-chip memory controller supporting up to 16 GBs of DRAM

- Maximum power consumption: 108 W at 1.35 V, 1.2 GHz

Get more details in the datasheet, including a block diagram of the
UltraSPARC IV processor:

Details at

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