Vol 71 Issue 1 2004-01-05 Article 11907 from section "Hardware"

Compatible with Sun[TM] Fireplane Interconnect, Solaris[TM] Operating System

In his article for Microprocessor Report, Kevin Krewell of In-Stat/MDR
examines the course Sun has set in its move toward chip-level
multithreading (CMT) with the UltraSPARC[R] IV processor, which he
describes as a pair of enhanced UltraSPARC[R] III cores sharing a
systems bus, DRAM memory controller and an off-die L2 cache. When Sun
migrates the manufacturing operations from the 130nm to the 90nm process
at Texas Instruments, the design will incorporate an on-die L2 cache and
the off-die cache will become a large L3 cache.

While the two cores share a single external L2 cache, each core has its
own on-chip cache tags. The external L2 SRAM can be up to 16 MB of
fault-tolerant chip kill DRAM per core, logically divided into two 8 MB
caches per core. The cache has 128-byte lines subdivided into two
64-byte subblocks that are two-way set-associative and have a
least-recently-used replacement policy. The cache bus uses fair dynamic
arbitration for bandwidth.

The two cores arbitrate for the shared system interface and can act as a
single Sun[TM] Fireplane interconnect client but support two interrupt
IDs (one per core). The Sun Fireplane interconnect bus has a
hierarchical address bus and is a point-to-point data bus to a data
switch that supports the two UltraSPARC processors.

Design of the UltraSPARC IV processor aims to leverage the
infrastructure and the system bus of the UltraSPARC III processor,
creating a stable platform that will enable on-site upgrades to numerous
Sun Fire[TM] systems.

Details at

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