This is a discussion on A thought about the IBM pSeries 750 - Solaris Rss ; When i looked at the technical overview draft redpieces of the p550 and the p750 a thought haunted me a little bit. The design of the p750 doesn't look to be really balanced. They put the faster CPUs in pretty ...
When i looked at the technical overview draft redpieces of the p550 and the p750 a thought haunted me a little bit. The design of the p750 doesn't look to be really balanced.
They put the faster CPUs in pretty much the same chassis. So I did a look at I/O subsystem numbers of both systems. The p550 and the p750 connects all it's busses (virtual ethernet, PCIe, PCI-X et al.) via an bridge chip. It's connected via an GX+ bridge to the CPUs and delivers 8.4 GB/sec (duplex). The p750 uses the same I/O chip and delivers 10 GByte/s (duplex). Given that the p750 has a much higher per system performance than the p550, at least the internal I/O subsystem wasn't extended as well to cope with the increased compute power.
I don't think that the design is balanced here. You need to suck the data from the disks or your network in order to process it. I would like to see a really I/O intensive benchmark to check this. At the moment it looks like a fast processor that waits very fast for data. At the moment i really think, that this proc is the DARPA HPC proc shoehorned into the old chassis to build some commercial servers out of it. IBM walked great length to make the memory subsystem more efficient (very useful for HPC), but the I/O part is somewhat underdeveloped in comparison.
Yes ... i know that the p750 has an accelerated second bus. It's called GX++ and it provides 20 GBytes/s duplex (10 GByte/s simplex) and you could use it to connect more I/O drawers. But you have to use the same cards to connect those drawers (12x DDR) to the p750 thus you reduce the bandwidth to same level as with the p550. Perhaps they will work on this point in the future.
BTW: The design looks to have a single point of failure, too, at least when you look at the architectural diagram on page 25 of the 750 technical overview. The P5IOC2 is just connected to one processor board. This chip delivers all "outside" connectivity. Would be interesting to know what happens, when the CPU board in first slot fail.