userspace access of physical memory and L1 cache
I'm working on a 32 bit powerpc embedded board based on xscale mpc8567 and Linux 126.96.36.199.
I have problems accessing device memory from user space through mmap() because of L1 data cache... here the details:
- If I write a single byte to the device from user-space I see 32 unwanted subsequent read accesses on the scope which eventually cause a major fault of the application software as those reads alter the device state.
- I really think those 32 accesses are due to L1 dcache as the cache line is actually 32 bytes :-)
- I've tried accessing the device both by mapping /dev/mem or implementing my own mmap() handler in the driver, which adjusts pgprot permissions (pgprot_nocache) and issue a remap_pfn_range but the result is all the same.
- The workaround is using read() and write() primitives on my char device which simply forwards the requests to the kernel that eventually issues an iowriteX call followed by a memory barrier.
The problem, besides performance issues, is that I cannot use read/write interface as this would make me trash all of the older code I must reuse :\
I thank you in advance for any suggestion,
Re: userspace access of physical memory and L1 cache
today I did some progress in understanding the problem.
It actually seems that the pages returned by io_remap_pfn_range() don't have the cache initbit bit while the ones returned by ioremap() do.
Since I'm using pgprot_noncached() macro on the vm_page_prot field before calling io_remap_pfn_range() i'd expect to have those bit set in the TLB entries.
I wonder if I've found a bug perhaps?
Thank you in advance!