Code to monitor cache hit rate? - Powerpc

This is a discussion on Code to monitor cache hit rate? - Powerpc ; Is there any linux code to monitor the L1 and L2 cache hit rates for the PPC 750 and 74xx? I would think so, but my google searches aren't turning up anything. Thanks, Matt...

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Thread: Code to monitor cache hit rate?

  1. Code to monitor cache hit rate?

    Is there any linux code to monitor the L1 and L2 cache hit rates for
    the PPC 750 and 74xx? I would think so, but my google searches aren't
    turning up anything.

    Thanks,

    Matt


  2. Re: Code to monitor cache hit rate?

    Matthew Clark wrote:

    > Is there any linux code to monitor the L1 and L2 cache hit rates for
    > the PPC 750 and 74xx? I would think so, but my google searches aren't
    > turning up anything.
    >


    I /think/ oprofile will let you capture data from the PMCs so that you
    can get cache hit rates and a zillion other bits of performance data.

    Paul

  3. Re: Code to monitor cache hit rate?

    Paul Russell wrote:
    > I /think/ oprofile will let you capture data from the PMCs so that you
    > can get cache hit rates and a zillion other bits of performance data.


    Thanks, Paul. I'll give that a try. I don't suppose oprofile can log
    ECC
    corrections in memory. I'm trying to stress this board using LTP and
    catch as much performance data as I can.

    Matt


  4. Re: Code to monitor cache hit rate?

    Matthew Clark wrote:

    > Paul Russell wrote:
    >
    >>I /think/ oprofile will let you capture data from the PMCs so that you
    >>can get cache hit rates and a zillion other bits of performance data.

    >
    >
    > Thanks, Paul. I'll give that a try. I don't suppose oprofile can log
    > ECC
    > corrections in memory. I'm trying to stress this board using LTP and
    > catch as much performance data as I can.
    >


    I'm not sure about ECC correction data - this is probably taken care of
    in the memory controller but you may still be able to get at a suitable
    register.

    Good luck,

    Paul

    P.S. On the 74xx if you really want to stress the board you'll want to
    keep the AltiVec units busy on the CPU - that can really drive up the
    power consumption and CPU core temperature etc.

  5. Re: Code to monitor cache hit rate?

    Paul,

    I'm using the "Stress" tests from the LTP. Do you think that'll be
    sufficient?

    Matt


  6. Re: Code to monitor cache hit rate?

    Matthew Clark wrote:

    > Paul,
    >
    > I'm using the "Stress" tests from the LTP. Do you think that'll be
    > sufficient?
    >


    I'm not familiar with LTP so I don't know if it has any 7400-specific
    code to exercise AltiVec. A good way to do this kind of thing is to run
    something AltiVec-optimised like a suitable MP3 encoder or MPEG video
    encoder. Let it run for an hour or two and maybe monitor the smbient and
    CPU core temperatures.

    Paul

  7. Re: Code to monitor cache hit rate?

    I got the ECC data ok (the board's bridge chip tracks it somehow), but
    Oprofiles appears to only act in timer mode on the PPC 74xx, no
    measurable performance counters. Any other ideas?


  8. Re: Code to monitor cache hit rate?

    Matthew Clark wrote:

    > I got the ECC data ok (the board's bridge chip tracks it somehow), but
    > Oprofiles appears to only act in timer mode on the PPC 74xx, no
    > measurable performance counters. Any other ideas?
    >


    Ah - sorry about that - you may just have to hack a bit of code together
    to read the PMCs.

    Paul

  9. Re: Code to monitor cache hit rate?

    "Matthew Clark" writes:
    >I got the ECC data ok (the board's bridge chip tracks it somehow), but
    >Oprofiles appears to only act in timer mode on the PPC 74xx, no
    >measurable performance counters. Any other ideas?


    Use the perfctr patch and associated tools, e.g., perfex.

    http://user.it.uu.se/~mikpe/linux/perfctr/
    http://www.complang.tuwien.ac.at/ant...x/ppc7450.html

    - anton
    --
    M. Anton Ertl Some things have to be seen to be believed
    anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen
    http://www.complang.tuwien.ac.at/anton/home.html

  10. Re: Code to monitor cache hit rate?

    Anton Ertl wrote:

    > "Matthew Clark" writes:
    >
    >>I got the ECC data ok (the board's bridge chip tracks it somehow), but
    >>Oprofiles appears to only act in timer mode on the PPC 74xx, no
    >>measurable performance counters. Any other ideas?

    >
    >
    > Use the perfctr patch and associated tools, e.g., perfex.
    >
    > http://user.it.uu.se/~mikpe/linux/perfctr/
    > http://www.complang.tuwien.ac.at/ant...x/ppc7450.html
    >


    Thanks Anton - that looks useful.

    Paul

  11. Re: Code to monitor cache hit rate?

    Yes, Anton. This is exactly what I'm looking for. Thanks!

    Matt


  12. Re: Code to monitor cache hit rate?

    Ok, next phase ;-)

    Anything out there that bangs on the PPC's L1/L2 cache and finds any
    parity errors? (A memtest for cache?)

    Matt


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