Reassign PCI device BARs to above 4GB by modifying kernel code? - Linux

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Thread: Reassign PCI device BARs to above 4GB by modifying kernel code?

  1. Reassign PCI device BARs to above 4GB by modifying kernel code?

    Is it possible to reassign the BARs of a PCI device through the
    kernel? I'd like to compile a test kernel that does just that. I
    believe that currently even if a PCI device does claim to support 64-
    bit BARs, the BIOS will still allocate the BARs under 4GB (at least I
    have such a BIOS) I want the kernel to reassign the BARs to > 4GB, and
    not depend on the BIOS to do that. Is this even possible? What part of
    the Linux kernel code does that?

    I suspect this is more complicated than simply writing a new BAR base
    into the PCI device's config space register.

    1) How do we ensure that we're not overlapping the physcal address
    space of any other PCI device when we choose a new BAR? Thinking about
    it, I guess we can use the physical address-space map that Linux gets
    with int15/E820h to see which physical memory areas are unused. Is
    that correct?

    2) I've just skimmed over the datasheet for one chipset controller,
    the Intel GMCH35. I think the "decode window" of the Host-PCI bridge
    in the chipset will also have to be reconfigured so that it will
    direct Host accesses to the new BAR range to the PCI express link. Or
    will it intercept config writes to the BAR portion of the PCI device's
    config space and update itself?

    Thanks in advance for your answers!
    -Mayank

  2. Re: Reassign PCI device BARs to above 4GB by modifying kernel code?

    mkaushik writes:
    > Is it possible to reassign the BARs of a PCI device through the
    > kernel?


    [...]

    > I suspect this is more complicated than simply writing a new BAR base
    > into the PCI device's config space register.


    Why would it? Linux supports platform without 'a BIOS' capable of
    doing anything with a PCI-bus.

    > 1) How do we ensure that we're not overlapping the physcal address
    > space of any other PCI device when we choose a new BAR?


    By using a suitable allocation algorithm. The 2.4.36-tree I have here
    contains a filed titled 'PCI autoconfiguration libray', originating
    from MontaVista, which is used to configure the PCI for an
    IXP425-based system. The basic allocation algorithm is to iterate over
    all bars of all devices and to allocate address space for each bar from a
    shrinking 'free space block', ie current base address is calculated as
    last base address minus bar size. The start value is take from a
    struct pci_controller passed as argument (simplified).

  3. Re: Reassign PCI device BARs to above 4GB by modifying kernel code?

    mkaushik wrote:
    >
    >Is it possible to reassign the BARs of a PCI device through the
    >kernel? I'd like to compile a test kernel that does just that. I
    >believe that currently even if a PCI device does claim to support 64-
    >bit BARs, the BIOS will still allocate the BARs under 4GB (at least I
    >have such a BIOS)


    Yes, and with good reason. As long as ANY PCI device needs a 32-bit BAR,
    the BIOS has to carve out a chunk of address space below 4GB to handle it.
    There is little incentive to carve out two different spaces, if one will
    do, and there is no benefit in doing so.
    --
    Tim Roberts, timr@probo.com
    Providenza & Boekelheide, Inc.

  4. Re: Reassign PCI device BARs to above 4GB by modifying kernel code?

    On Nov 9, 5:45*am, Tim Roberts wrote:
    > mkaushik wrote:
    >
    > >Is it possible to reassign the BARs of a PCI device through the
    > >kernel? I'd like to compile a test kernel that does just that. I
    > >believe that currently even if a PCI device does claim to support 64-
    > >bit BARs, the BIOS will still allocate the BARs under 4GB (at least I
    > >have such a BIOS)

    >
    > Yes, and with good reason. *As long as ANY PCI device needs a 32-bit BAR,
    > the BIOS has to carve out a chunk of address space below 4GB to handle it..
    > There is little incentive to carve out two different spaces, if one will
    > do, and there is no benefit in doing so.


    Not really, I'm running into a situation where I need to support lots
    of PCI devices in the same system. Each one of them claims some BAR
    space, so if the BIOS tries to stuff all of them below 4GB, some of
    the PCI devices just wont be usable.

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