(CHARSET: PC-8)
(PATH: 263/950 236/150 261/38 140/1 106/2000 123/500 3613/1275 134/10)
From: "Tavis Ormandy"

(CHARSET: PC-8)
(PATH: 263/950 236/150 261/38 140/1 106/2000 123/500 3613/1275 134/10) From:
"Tavis Ormandy"

(CHARSET: PC-8)
(PATH: 263/950 236/150 261/38 140/1 106/2000 123/500 3613/1275 134/10) From:
"Tavis Ormandy"

(CHARSET: PC-8)
(PATH: 263/950 236/150 261/38 140/1 106/2000 123/500 3613/1275 134/10) From:
Tavis Ormandy

the gcc scheduler uses memory latency timings to predict optimal scheduling
for memory references, the man page says that gcc knows typical timings for
ev4 and ev5..thats cool, but id like specific timings for my machines so the
scheduler can do the best job possible.

so i snarfed the source and investigated where it gets these figures from and
how it uses them...this is what i found:

* gcc has 9 values hardcoded
L1 and L2 (and a rogue value for L3) for ev4.
L1, L2 and L3 for ev5 and ev6.
an estimate of `main` memory latency.

* if you dont specify a memory latency, it uses its hardcoded value
for L1 on your revision.

* if you specify a bogus latency, it assumes 3 cycles

okay, these are the figures it has (this is gcc 3.2.3 btw)

static int const cache_latency[][4] =
{
{ 3, 30, -1 }, /* <-- ev4 */
{ 2, 12, 38 }, /* <-- ev5 */
{ 3, 12, 30 }, /* <-- ev6 */
}

/* ... */

else if (! strcmp (alpha_mlat_string, "main"))
lat = 150;

the comments say that the authors machine's main memory has latency of 370ns,
so if i understand this..

(((150/370)*10^9)/10^6) == 405Mhz

so assuming this guy made the timings for the ev5 Dcache latency as well,
using the same machine..

((10^9/405Mhz)*2) == 4.938ns latency of his Dcache (which sounds
about right)

(please correct me if im way off here, btw)

so i benchmarked mine, and my Dcache has a latency of 3.799 nanoseconds, and
my ruffian has a 533Mhz clock speed, so my
-mmemory-latency time should be

(3.799/(10^9/533Mhz)) == 2 cycles, which works (although i
seem to get better benchmarks with 3 cycles latency...).

the value for `main` also works (well, 2 cycles out), so apply the same logic
to the Scache, where i have a latency of 65.1 ns

(65.1/(10^9/533Mhz)) == 34.71 ...

so where is this 12 cycles figure coming from? id be greatful if anyone can
explain it.

--
-------------------------------------
taviso@sdf.lonestar.org | finger me for my gpg key.
-------------------------------------------------------

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