[PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition - Kernel

This is a discussion on [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition - Kernel ; Hi, These patches define a framework for hypervisor detection and setting of hypervisor feature bits. We define a X86_FEATURE_TSC_RELIABLE bit which is a synthetic bit. This is set when running under VMware. This feature bit is used to skip TSC ...

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Thread: [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition

  1. [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition

    Hi,

    These patches define a framework for hypervisor detection and setting of
    hypervisor feature bits. We define a X86_FEATURE_TSC_RELIABLE bit which
    is a synthetic bit. This is set when running under VMware. This feature
    bit is used to skip TSC checks which can fail on virtualization platform
    due to timing differences when running on virtual cpus.

    Thanks,
    Alok


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  2. Re: [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition


    * Alok Kataria wrote:

    > Hi,
    >
    > These patches define a framework for hypervisor detection and
    > setting of hypervisor feature bits. We define a
    > X86_FEATURE_TSC_RELIABLE bit which is a synthetic bit. This is set
    > when running under VMware. This feature bit is used to skip TSC
    > checks which can fail on virtualization platform due to timing
    > differences when running on virtual cpus.


    okay, this looks a lot better structurally - the DMI angle and the
    synthetic CPU flag, and the clocksource smarts are all a clean
    approach. Peter, any objections?

    Ingo
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