Re: [PATCH] x86: do not allow to optimize flag_is_changeable_p() - Kernel

This is a discussion on Re: [PATCH] x86: do not allow to optimize flag_is_changeable_p() - Kernel ; > Yinghai Lu wrote: > > On Mon, Sep 29, 2008 at 11:14 PM, Jeremy Fitzhardinge > wrote: > > > >> Krzysztof Helt wrote: > >> > >>> From: Krzysztof Helt > >>> > >>> The flag_is_changeable_p() is used ...

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Thread: Re: [PATCH] x86: do not allow to optimize flag_is_changeable_p()

  1. Re: [PATCH] x86: do not allow to optimize flag_is_changeable_p()

    > Yinghai Lu wrote:
    > > On Mon, Sep 29, 2008 at 11:14 PM, Jeremy Fitzhardinge

    > wrote:
    > >
    > >> Krzysztof Helt wrote:
    > >>
    > >>> From: Krzysztof Helt
    > >>>
    > >>> The flag_is_changeable_p() is used by
    > >>> has_cpuid_p() which can return different results
    > >>> in the code sequence below:
    > >>>
    > >>> if (!have_cpuid_p())
    > >>> identify_cpu_without_cpuid(c);
    > >>>
    > >>> /* cyrix could have cpuid enabled via c_identify()*/
    > >>> if (!have_cpuid_p())
    > >>> return;
    > >>>
    > >>> Otherwise, the gcc 3.4.6 optimizes these two calls
    > >>> into one which make the code not working correctly.
    > >>> Cyrix cpus have the CPUID instruction enabled but
    > >>> it is not detected due to the gcc optimization.
    > >>> Thus the ARR registers (mtrr like) are not detected
    > >>> on such a cpu.
    > >>>
    > >>>
    > >> If "asm volatile" changes the code and fixes the bug, it seems like
    > >> you're making use of an undocumented - or at least non-portable -

    > behaviour.
    > >>


    Why you call it undocumented. This is information you can find with "info gcc" in the Extendend Asm section:

    If your assembler instructions access memory in an unpredictable
    fashion, add `memory' to the list of clobbered registers. This will
    cause GCC to not keep memory values cached in registers across the
    assembler instruction and not optimize stores or loads to that memory.
    You will also want to add the `volatile' keyword if the memory affected
    is not listed in the inputs or outputs of the `asm', as the `memory'
    clobber does not count as a side-effect of the `asm'. If you know how
    large the accessed memory is, you can add it as input or output but if
    this is not known, you should add `memory'.

    > >> Does adding a "memory" clobber also fix the problem? That would have
    > >> better defined characteristics.
    > >>


    A changeable flag bit is hardly a memory side effect. IMO, the volatile attribute is better as it says that each evaluation may have a different results despite the inputs and outputs are the same.

    >
    > The trouble is that flag_is_changeable_p() doesn't have any obvious
    > global dependencies; it just takes a constant argument and returns a
    > result. The asm() needs to be updated to have a "memory" constraint as
    > a stand-in for the specific constraint of "cpu has switched into
    > cpuid-supporting state".
    >


    See above about adding the memory constrain.

    Kind regards,
    Krzysztof

    ----------------------------------------------------------------------
    Tanie i proste polaczenia telefoniczne!
    Sprawdz >> http://link.interia.pl/f1f23


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  2. Re: [PATCH] x86: do not allow to optimize flag_is_changeable_p()

    krzysztof.h1@poczta.fm wrote:
    > If your assembler instructions access memory in an unpredictable
    > fashion, add `memory' to the list of clobbered registers. This will
    > cause GCC to not keep memory values cached in registers across the
    > assembler instruction and not optimize stores or loads to that memory.
    > You will also want to add the `volatile' keyword if the memory affected
    > is not listed in the inputs or outputs of the `asm', as the `memory'
    > clobber does not count as a side-effect of the `asm'. If you know how
    > large the accessed memory is, you can add it as input or output but if
    > this is not known, you should add `memory'.
    >


    Yes, you're right. The pertinent part of the manual is:

    The `volatile' keyword indicates that the instruction has important
    side-effects. GCC will not delete a volatile `asm' if it is reachable.
    (The instruction can still be deleted if GCC can prove that
    control-flow will never reach the location of the instruction.) Note
    that even a volatile `asm' instruction can be moved relative to other
    code, including across jump instructions.


    I normally do my "asm volatile" rant when people try to use it to
    enforce ordering, but in this case we just want gcc to not elide the
    second use.

    So, yes, I think your patch is fine as-is, but it would be worth adding
    a comment on the asm (its not necessarily obvious that the
    cpuid-capability of a cpu can change).

    J
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