[PATCH 1/5] FRV: Handle update_mmu_cache() being called when current->mm is NULL [try #2] - Kernel

This is a discussion on [PATCH 1/5] FRV: Handle update_mmu_cache() being called when current->mm is NULL [try #2] - Kernel ; From: David Howells Handle update_mmu_cache() being called when current->mm is NULL. We cache static TLB mappings for the current page table in DAMPR4 and DAMPR5 on the theory that the next data lookup is likely to be in the same ...

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Thread: [PATCH 1/5] FRV: Handle update_mmu_cache() being called when current->mm is NULL [try #2]

  1. [PATCH 1/5] FRV: Handle update_mmu_cache() being called when current->mm is NULL [try #2]

    From: David Howells

    Handle update_mmu_cache() being called when current->mm is NULL.

    We cache static TLB mappings for the current page table in DAMPR4 and DAMPR5
    on the theory that the next data lookup is likely to be in the same general
    region, and thus is likely to be mapped by the same page table. However, we
    can't get this information if we can't access the appropriate mm_struct.

    If current->mm is NULL, we just clear the cache in the knowledge that the TLB
    miss handlers will load it.

    Signed-off-by: David Howells
    ---

    include/asm-frv/pgtable.h | 19 ++++++++++++++-----
    1 files changed, 14 insertions(+), 5 deletions(-)


    diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h
    index 6c0682e..4e21904 100644
    --- a/include/asm-frv/pgtable.h
    +++ b/include/asm-frv/pgtable.h
    @@ -507,13 +507,22 @@ static inline int pte_file(pte_t pte)
    */
    static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
    {
    + struct mm_struct *mm;
    unsigned long ampr;
    - pgd_t *pge = pgd_offset(current->mm, address);
    - pud_t *pue = pud_offset(pge, address);
    - pmd_t *pme = pmd_offset(pue, address);

    - ampr = pme->ste[0] & 0xffffff00;
    - ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C | xAMPRx_V;
    + mm = current->mm;
    + if (mm) {
    + pgd_t *pge = pgd_offset(mm, address);
    + pud_t *pue = pud_offset(pge, address);
    + pmd_t *pme = pmd_offset(pue, address);
    +
    + ampr = pme->ste[0] & 0xffffff00;
    + ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C |
    + xAMPRx_V;
    + } else {
    + address = ULONG_MAX;
    + ampr = 0;
    + }

    asm volatile("movgs %0,scr0\n"
    "movgs %0,scr1\n"

    --
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  2. [PATCH 4/5] FRV: Make NOMMU-mode work with base addresses other than 0xC0000000 [try #2]

    From: David Howells

    Make NOMMU-mode work with base addresses other than 0xC0000000 by:

    (1) Giving the code that sets up the protection registers the right address
    in __sdram_base. Rather than being hard coded to 0xC0000000, the value
    of __page_offset is obtained from the linker script.

    (2) Eliminate the check in __switch_to() that verifies the current thread
    info is in the 0xCxxxxxxx region.

    Signed-off-by: David Howells
    ---

    arch/frv/kernel/head.inc | 2 +-
    arch/frv/kernel/switch_to.S | 7 -------
    2 files changed, 1 insertions(+), 8 deletions(-)


    diff --git a/arch/frv/kernel/head.inc b/arch/frv/kernel/head.inc
    index d424cd2..bff6662 100644
    --- a/arch/frv/kernel/head.inc
    +++ b/arch/frv/kernel/head.inc
    @@ -46,5 +46,5 @@
    #ifdef CONFIG_MMU
    __sdram_base = 0x00000000 /* base address to which SDRAM relocated */
    #else
    -__sdram_base = 0xc0000000 /* base address to which SDRAM relocated */
    +__sdram_base = __page_offset /* base address to which SDRAM relocated */
    #endif
    diff --git a/arch/frv/kernel/switch_to.S b/arch/frv/kernel/switch_to.S
    index b5275fa..b066686 100644
    --- a/arch/frv/kernel/switch_to.S
    +++ b/arch/frv/kernel/switch_to.S
    @@ -102,13 +102,6 @@ __switch_to:
    movgs gr14,lr
    bar

    - srli gr15,#28,gr5
    - subicc gr5,#0xc,gr0,icc0
    - beq icc0,#0,111f
    - break
    - nop
    -111:
    -
    # jump to __switch_back or ret_from_fork as appropriate
    # - move prev to GR8
    movgs gr4,psr

    --
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