[PATCH 0/79] smpboot integration - Kernel

This is a discussion on [PATCH 0/79] smpboot integration - Kernel ; Hi, This is a complement to my last patch series. In this one, I integrate smpboot.c The end result is that i386 also uses the new hotplug state machine, and boot cpus via cpu_up, instead of booting them in the ...

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  1. [PATCH 0/79] smpboot integration

    Hi,

    This is a complement to my last patch series. In this one, I integrate smpboot.c
    The end result is that i386 also uses the new hotplug state machine, and boot cpus
    via cpu_up, instead of booting them in the preparation step, and only activating later.

    The final diffstat says:
    59 files changed, 1974 insertions(+), 2752 deletions(-)

    Leftovers:

    smp.h could also be easily integrated. But this series was too big already
    setup64.c could also be completely moved to setup.c

    Testing and bisectability:

    The end result was tested in all my hardware (which includes qemu ;-).
    It does not mean it will boot _your_ hardware, but I did my best ;-)

    The tree at least compiles in more than 20 randconfigs (for each of x86_64 and i386)
    For i386, each of the subarchitectures was compiled at least once. (By compile, I obviously
    mean, every patch, individually)

    Full diffstat:

    a/arch/x86/kernel/smpboot_32.c | 68 -
    a/arch/x86/kernel/smpboot_64.c | 73 -
    a/include/asm-x86/nmi_64.h | 89 -
    arch/x86/kernel/Makefile | 4
    arch/x86/kernel/apic_32.c | 81 -
    arch/x86/kernel/mpparse_32.c | 19
    arch/x86/kernel/mpparse_64.c | 12
    arch/x86/kernel/nmi_32.c | 2
    arch/x86/kernel/smpboot.c | 1071 ++++++++++++++++
    arch/x86/kernel/smpboot_32.c | 1617 ++++---------------------
    arch/x86/kernel/smpboot_64.c | 949 +-------------
    b/arch/x86/Kconfig | 2
    b/arch/x86/Makefile | 2
    b/arch/x86/kernel/Makefile | 2
    b/arch/x86/kernel/acpi/boot.c | 2
    b/arch/x86/kernel/apic_32.c | 23
    b/arch/x86/kernel/apic_64.c | 13
    b/arch/x86/kernel/bugs_64.c | 3
    b/arch/x86/kernel/mpparse_32.c | 12
    b/arch/x86/kernel/mpparse_64.c | 2
    b/arch/x86/kernel/nmi_32.c | 2
    b/arch/x86/kernel/nmi_64.c | 2
    b/arch/x86/kernel/process_32.c | 10
    b/arch/x86/kernel/setup.c | 103 +
    b/arch/x86/kernel/setup64.c | 77 -
    b/arch/x86/kernel/setup_32.c | 25
    b/arch/x86/kernel/setup_64.c | 15
    b/arch/x86/kernel/smpboot.c | 77 +
    b/arch/x86/kernel/smpboot_32.c | 5
    b/arch/x86/kernel/smpboot_64.c | 19
    b/arch/x86/kernel/traps_64.c | 2
    b/arch/x86/mach-voyager/voyager_smp.c | 7
    b/arch/x86/mm/k8topology_64.c | 7
    b/arch/x86/pci/numa.c | 8
    b/arch/x86/vdso/Makefile | 2
    b/include/asm-x86/apic.h | 3
    b/include/asm-x86/apicdef.h | 7
    b/include/asm-x86/mach-bigsmp/mach_apic.h | 7
    b/include/asm-x86/mach-default/mach_apic.h | 11
    b/include/asm-x86/mach-default/mach_apicdef.h | 5
    b/include/asm-x86/mach-default/smpboot_hooks.h | 3
    b/include/asm-x86/mach-es7000/mach_apic.h | 8
    b/include/asm-x86/mach-summit/mach_apic.h | 4
    b/include/asm-x86/mach-visws/smpboot_hooks.h | 5
    b/include/asm-x86/mmzone_32.h | 3
    b/include/asm-x86/nmi.h | 92 +
    b/include/asm-x86/nmi_64.h | 3
    b/include/asm-x86/smp.h | 3
    b/include/asm-x86/smp_32.h | 5
    b/include/asm-x86/smp_64.h | 12
    b/include/asm-x86/topology.h | 9
    include/asm-x86/apic.h | 2
    include/asm-x86/apicdef.h | 6
    include/asm-x86/mach-default/smpboot_hooks.h | 5
    include/asm-x86/nmi.h | 5
    include/asm-x86/nmi_32.h | 61
    include/asm-x86/smp.h | 29
    include/asm-x86/smp_32.h | 16
    include/asm-x86/smp_64.h | 15
    59 files changed, 1974 insertions(+), 2752 deletions(-)


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  2. [PATCH 10/79] [PATCH] merge smp_store_cpu_info

    From: Glauber Costa

    now that it is the same between arches, put it into smpboot.c

    Signed-off-by: Glauber Costa
    ---
    arch/x86/kernel/smpboot.c | 77 ++++++++++++++++++++++++++++++++++++++++++
    arch/x86/kernel/smpboot_32.c | 71 +--------------------------------------
    arch/x86/kernel/smpboot_64.c | 15 --------
    include/asm-x86/smp.h | 2 +
    include/asm-x86/smp_32.h | 2 -
    5 files changed, 80 insertions(+), 87 deletions(-)

    diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
    index b13b9d5..a157a52 100644
    --- a/arch/x86/kernel/smpboot.c
    +++ b/arch/x86/kernel/smpboot.c
    @@ -45,6 +45,83 @@ unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
    /* representing cpus for which sibling maps can be computed */
    static cpumask_t cpu_sibling_setup_map;

    +#ifdef CONFIG_X86_32
    +/* Set if we find a B stepping CPU */
    +int __cpuinitdata smp_b_stepping;
    +#endif
    +
    +static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
    +{
    +#ifdef CONFIG_X86_32
    + /*
    + * Mask B, Pentium, but not Pentium MMX
    + */
    + if (c->x86_vendor == X86_VENDOR_INTEL &&
    + c->x86 == 5 &&
    + c->x86_mask >= 1 && c->x86_mask <= 4 &&
    + c->x86_model <= 3)
    + /*
    + * Remember we have B step Pentia with bugs
    + */
    + smp_b_stepping = 1;
    +
    + /*
    + * Certain Athlons might work (for various values of 'work') in SMP
    + * but they are not certified as MP capable.
    + */
    + if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
    +
    + if (num_possible_cpus() == 1)
    + goto valid_k7;
    +
    + /* Athlon 660/661 is valid. */
    + if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
    + (c->x86_mask == 1)))
    + goto valid_k7;
    +
    + /* Duron 670 is valid */
    + if ((c->x86_model == 7) && (c->x86_mask == 0))
    + goto valid_k7;
    +
    + /*
    + * Athlon 662, Duron 671, and Athlon >model 7 have capability
    + * bit. It's worth noting that the A5 stepping (662) of some
    + * Athlon XP's have the MP bit set.
    + * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
    + * more.
    + */
    + if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
    + ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
    + (c->x86_model > 7))
    + if (cpu_has_mp)
    + goto valid_k7;
    +
    + /* If we get here, not a certified SMP capable AMD system. */
    + add_taint(TAINT_UNSAFE_SMP);
    + }
    +
    +valid_k7:
    + ;
    +#endif
    +}
    +
    +/*
    + * The bootstrap kernel entry code has set these up. Save them for
    + * a given CPU
    + */
    +
    +void __cpuinit smp_store_cpu_info(int id)
    +{
    + struct cpuinfo_x86 *c = &cpu_data(id);
    +
    + *c = boot_cpu_data;
    + c->cpu_index = id;
    + if (id != 0)
    + identify_secondary_cpu(c);
    + smp_apply_quirks(c);
    +}
    +
    +
    void __cpuinit set_cpu_sibling_map(int cpu)
    {
    int i;
    diff --git a/arch/x86/kernel/smpboot_32.c b/arch/x86/kernel/smpboot_32.c
    index e050064..0bfb31e 100644
    --- a/arch/x86/kernel/smpboot_32.c
    +++ b/arch/x86/kernel/smpboot_32.c
    @@ -59,8 +59,7 @@
    #include
    #include

    -/* Set if we find a B stepping CPU */
    -static int __cpuinitdata smp_b_stepping;
    +extern int smp_b_stepping;

    static cpumask_t smp_commenced_mask;

    @@ -78,74 +77,6 @@ static void map_cpu_to_logical_apicid(void);
    /* State of each CPU. */
    DEFINE_PER_CPU(int, cpu_state) = { 0 };

    -static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
    -{
    - /*
    - * Mask B, Pentium, but not Pentium MMX
    - */
    - if (c->x86_vendor == X86_VENDOR_INTEL &&
    - c->x86 == 5 &&
    - c->x86_mask >= 1 && c->x86_mask <= 4 &&
    - c->x86_model <= 3)
    - /*
    - * Remember we have B step Pentia with bugs
    - */
    - smp_b_stepping = 1;
    -
    - /*
    - * Certain Athlons might work (for various values of 'work') in SMP
    - * but they are not certified as MP capable.
    - */
    - if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
    -
    - if (num_possible_cpus() == 1)
    - goto valid_k7;
    -
    - /* Athlon 660/661 is valid. */
    - if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
    - goto valid_k7;
    -
    - /* Duron 670 is valid */
    - if ((c->x86_model==7) && (c->x86_mask==0))
    - goto valid_k7;
    -
    - /*
    - * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
    - * It's worth noting that the A5 stepping (662) of some Athlon XP's
    - * have the MP bit set.
    - * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
    - */
    - if (((c->x86_model==6) && (c->x86_mask>=2)) ||
    - ((c->x86_model==7) && (c->x86_mask>=1)) ||
    - (c->x86_model> 7))
    - if (cpu_has_mp)
    - goto valid_k7;
    -
    - /* If we get here, it's not a certified SMP capable AMD system. */
    - add_taint(TAINT_UNSAFE_SMP);
    - }
    -
    -valid_k7:
    - ;
    -
    -}
    -
    -/*
    - * The bootstrap kernel entry code has set these up. Save them for
    - * a given CPU
    - */
    -
    -void __cpuinit smp_store_cpu_info(int id)
    -{
    - struct cpuinfo_x86 *c = &cpu_data(id);
    -
    - *c = boot_cpu_data;
    - c->cpu_index = id;
    - if (id != 0)
    - identify_secondary_cpu(c);
    - smp_apply_quirks(c);
    -}
    -
    static atomic_t init_deasserted;

    static void __cpuinit smp_callin(void)
    diff --git a/arch/x86/kernel/smpboot_64.c b/arch/x86/kernel/smpboot_64.c
    index f84e30d..c213345 100644
    --- a/arch/x86/kernel/smpboot_64.c
    +++ b/arch/x86/kernel/smpboot_64.c
    @@ -85,21 +85,6 @@ struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
    #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p))
    #endif

    -/*
    - * The bootstrap kernel entry code has set these up. Save them for
    - * a given CPU
    - */
    -
    -static void __cpuinit smp_store_cpu_info(int id)
    -{
    - struct cpuinfo_x86 *c = &cpu_data(id);
    -
    - *c = boot_cpu_data;
    - c->cpu_index = id;
    - if (id != 0)
    - identify_secondary_cpu(c);
    -}
    -
    static inline void wait_for_init_deassert(atomic_t *deassert)
    {
    while (!atomic_read(deassert))
    diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h
    index 4dc271b..b4c5143 100644
    --- a/include/asm-x86/smp.h
    +++ b/include/asm-x86/smp.h
    @@ -88,6 +88,8 @@ extern void prefill_possible_map(void);

    #define SMP_TRAMPOLINE_BASE 0x6000
    extern unsigned long setup_trampoline(void);
    +
    +void smp_store_cpu_info(int id);
    #endif

    #ifdef CONFIG_X86_32
    diff --git a/include/asm-x86/smp_32.h b/include/asm-x86/smp_32.h
    index 76740de..51624ab 100644
    --- a/include/asm-x86/smp_32.h
    +++ b/include/asm-x86/smp_32.h
    @@ -42,8 +42,6 @@ DECLARE_PER_CPU(int, cpu_number);

    extern int safe_smp_processor_id(void);

    -void __cpuinit smp_store_cpu_info(int id);
    -
    /* We don't mark CPUs online until __cpu_up(), so we need another measure */
    static inline int num_booting_cpus(void)
    {
    --
    1.5.0.6

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  3. [PATCH 24/79] [PATCH] define bios to apicid mapping

    From: Glauber Costa

    This mapping already exists in x86_64, just provide it for
    i386

    Signed-off-by: Glauber Costa
    ---
    arch/x86/kernel/smpboot_32.c | 6 ++++++
    include/asm-x86/mach-bigsmp/mach_apic.h | 7 ++-----
    include/asm-x86/mach-es7000/mach_apic.h | 8 +++-----
    include/asm-x86/mach-summit/mach_apic.h | 3 +--
    4 files changed, 12 insertions(+), 12 deletions(-)

    diff --git a/arch/x86/kernel/smpboot_32.c b/arch/x86/kernel/smpboot_32.c
    index 0e86ccc..92a5df6 100644
    --- a/arch/x86/kernel/smpboot_32.c
    +++ b/arch/x86/kernel/smpboot_32.c
    @@ -70,6 +70,12 @@ void *x86_cpu_to_apicid_early_ptr;
    DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID;
    EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid);

    +u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
    + = { [0 ... NR_CPUS-1] = BAD_APICID };
    +void *x86_bios_cpu_apicid_early_ptr;
    +DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
    +EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
    +
    u8 apicid_2_node[MAX_APICID];

    static void map_cpu_to_logical_apicid(void);
    diff --git a/include/asm-x86/mach-bigsmp/mach_apic.h b/include/asm-x86/mach-bigsmp/mach_apic.h
    index 6df235e..0d55b1f 100644
    --- a/include/asm-x86/mach-bigsmp/mach_apic.h
    +++ b/include/asm-x86/mach-bigsmp/mach_apic.h
    @@ -1,10 +1,7 @@
    #ifndef __ASM_MACH_APIC_H
    #define __ASM_MACH_APIC_H

    -
    -extern u8 bios_cpu_apicid[];
    -
    -#define xapic_phys_to_log_apicid(cpu) (bios_cpu_apicid[cpu])
    +#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
    #define esr_disable (1)

    static inline int apic_id_registered(void)
    @@ -90,7 +87,7 @@ static inline int apicid_to_node(int logical_apicid)
    static inline int cpu_present_to_apicid(int mps_cpu)
    {
    if (mps_cpu < NR_CPUS)
    - return (int) bios_cpu_apicid[mps_cpu];
    + return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);

    return BAD_APICID;
    }
    diff --git a/include/asm-x86/mach-es7000/mach_apic.h b/include/asm-x86/mach-es7000/mach_apic.h
    index d23011f..04cba9f 100644
    --- a/include/asm-x86/mach-es7000/mach_apic.h
    +++ b/include/asm-x86/mach-es7000/mach_apic.h
    @@ -1,9 +1,7 @@
    #ifndef __ASM_MACH_APIC_H
    #define __ASM_MACH_APIC_H

    -extern u8 bios_cpu_apicid[];
    -
    -#define xapic_phys_to_log_apicid(cpu) (bios_cpu_apicid[cpu])
    +#define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
    #define esr_disable (1)

    static inline int apic_id_registered(void)
    @@ -80,7 +78,7 @@ extern void enable_apic_mode(void);
    extern int apic_version [MAX_APICS];
    static inline void setup_apic_routing(void)
    {
    - int apic = bios_cpu_apicid[smp_processor_id()];
    + int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
    printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
    (apic_version[apic] == 0x14) ?
    "Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]);
    @@ -102,7 +100,7 @@ static inline int cpu_present_to_apicid(int mps_cpu)
    if (!mps_cpu)
    return boot_cpu_physical_apicid;
    else if (mps_cpu < NR_CPUS)
    - return (int) bios_cpu_apicid[mps_cpu];
    + return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
    else
    return BAD_APICID;
    }
    diff --git a/include/asm-x86/mach-summit/mach_apic.h b/include/asm-x86/mach-summit/mach_apic.h
    index 062c97f..91d7641 100644
    --- a/include/asm-x86/mach-summit/mach_apic.h
    +++ b/include/asm-x86/mach-summit/mach_apic.h
    @@ -40,7 +40,6 @@ static inline unsigned long check_apicid_present(int bit)

    #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)

    -extern u8 bios_cpu_apicid[];
    extern u8 cpu_2_logical_apicid[];

    static inline void init_apic_ldr(void)
    @@ -110,7 +109,7 @@ static inline int cpu_to_logical_apicid(int cpu)
    static inline int cpu_present_to_apicid(int mps_cpu)
    {
    if (mps_cpu < NR_CPUS)
    - return (int)bios_cpu_apicid[mps_cpu];
    + return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
    else
    return BAD_APICID;
    }
    --
    1.5.0.6

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  4. [PATCH 23/79] [PATCH] unify extern masks declaration

    From: Glauber Costa

    take them off smp_{32,64}.h and move to smp.h

    Signed-off-by: Glauber Costa
    ---
    include/asm-x86/smp.h | 12 ++++++++++++
    include/asm-x86/smp_32.h | 8 --------
    include/asm-x86/smp_64.h | 11 -----------
    3 files changed, 12 insertions(+), 19 deletions(-)

    diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h
    index b4c5143..d02e6ea 100644
    --- a/include/asm-x86/smp.h
    +++ b/include/asm-x86/smp.h
    @@ -3,12 +3,24 @@
    #ifndef __ASSEMBLY__
    #include
    #include
    +#include

    extern cpumask_t cpu_callout_map;

    extern int smp_num_siblings;
    extern unsigned int num_processors;

    +extern u16 x86_cpu_to_apicid_init[];
    +extern u16 x86_bios_cpu_apicid_init[];
    +extern void *x86_cpu_to_apicid_early_ptr;
    +extern void *x86_bios_cpu_apicid_early_ptr;
    +
    +DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
    +DECLARE_PER_CPU(cpumask_t, cpu_core_map);
    +DECLARE_PER_CPU(u16, cpu_llc_id);
    +DECLARE_PER_CPU(u16, x86_cpu_to_apicid);
    +DECLARE_PER_CPU(u16, x86_bios_cpu_apicid);
    +
    /*
    * Trampoline 80x86 program as an array.
    */
    diff --git a/include/asm-x86/smp_32.h b/include/asm-x86/smp_32.h
    index 51624ab..478f556 100644
    --- a/include/asm-x86/smp_32.h
    +++ b/include/asm-x86/smp_32.h
    @@ -21,14 +21,6 @@ extern cpumask_t cpu_callin_map;
    extern void (*mtrr_hook) (void);
    extern void zap_low_mappings (void);

    -extern u16 __initdata x86_cpu_to_apicid_init[];
    -extern void *x86_cpu_to_apicid_early_ptr;
    -
    -DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
    -DECLARE_PER_CPU(cpumask_t, cpu_core_map);
    -DECLARE_PER_CPU(u16, cpu_llc_id);
    -DECLARE_PER_CPU(u16, x86_cpu_to_apicid);
    -
    #ifdef CONFIG_SMP
    /*
    * This function is needed by all SMP systems. It must _always_ be valid
    diff --git a/include/asm-x86/smp_64.h b/include/asm-x86/smp_64.h
    index 394c785..1b3c0f1 100644
    --- a/include/asm-x86/smp_64.h
    +++ b/include/asm-x86/smp_64.h
    @@ -19,17 +19,6 @@ extern cpumask_t cpu_callin_map;
    extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
    void *info, int wait);

    -extern u16 __initdata x86_cpu_to_apicid_init[];
    -extern u16 __initdata x86_bios_cpu_apicid_init[];
    -extern void *x86_cpu_to_apicid_early_ptr;
    -extern void *x86_bios_cpu_apicid_early_ptr;
    -
    -DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
    -DECLARE_PER_CPU(cpumask_t, cpu_core_map);
    -DECLARE_PER_CPU(u16, cpu_llc_id);
    -DECLARE_PER_CPU(u16, x86_cpu_to_apicid);
    -DECLARE_PER_CPU(u16, x86_bios_cpu_apicid);
    -
    static inline int cpu_present_to_apicid(int mps_cpu)
    {
    if (cpu_present(mps_cpu))
    --
    1.5.0.6

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  5. [PATCH 28/79] [PATCH] use specialized routine for setup per-cpu area

    From: Glauber Costa

    We use the same routing as x86_64, moved now to setup.c.
    Just with a few ifdefs inside.
    Note that this routing uses prefill_possible_map().
    It has the very nice side effect of allowing hotplugging of
    cpus that are marked as present but disabled by acpi bios.

    Signed-off-by: Glauber Costa
    ---
    arch/x86/Kconfig | 2 +-
    arch/x86/kernel/Makefile | 2 +-
    arch/x86/kernel/setup.c | 103 ++++++++++++++++++++++++++++++++++++++++++
    arch/x86/kernel/setup64.c | 77 -------------------------------
    arch/x86/kernel/smpboot_32.c | 2 +
    5 files changed, 107 insertions(+), 79 deletions(-)
    create mode 100644 arch/x86/kernel/setup.c

    diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
    index a234ce9..5f1f381 100644
    --- a/arch/x86/Kconfig
    +++ b/arch/x86/Kconfig
    @@ -121,7 +121,7 @@ config ARCH_HAS_CPU_RELAX
    def_bool y

    config HAVE_SETUP_PER_CPU_AREA
    - def_bool X86_64
    + def_bool X86_64 || (X86_SMP && !X86_VOYAGER)

    config ARCH_HIBERNATION_POSSIBLE
    def_bool y
    diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
    index 09b7b4e..dc333c8 100644
    --- a/arch/x86/kernel/Makefile
    +++ b/arch/x86/kernel/Makefile
    @@ -19,7 +19,7 @@ CFLAGS_paravirt.o := $(nostackp)
    obj-y := process_$(BITS).o signal_$(BITS).o entry_$(BITS).o
    obj-y += traps_$(BITS).o irq_$(BITS).o
    obj-y += time_$(BITS).o ioport.o ldt.o
    -obj-y += setup_$(BITS).o i8259_$(BITS).o
    +obj-y += setup_$(BITS).o i8259_$(BITS).o setup.o
    obj-$(CONFIG_X86_32) += sys_i386_32.o i386_ksyms_32.o
    obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o
    obj-$(CONFIG_X86_64) += syscall_64.o vsyscall_64.o setup64.o
    diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
    new file mode 100644
    index 0000000..1179aa0
    --- /dev/null
    +++ b/arch/x86/kernel/setup.c
    @@ -0,0 +1,103 @@
    +#include
    +#include
    +#include
    +#include
    +#include
    +#include
    +#include
    +#include
    +#include
    +#include
    +#include
    +
    +#ifdef CONFIG_HAVE_SETUP_PER_CPU_AREA
    +/*
    + * Copy data used in early init routines from the initial arrays to the
    + * per cpu data areas. These arrays then become expendable and the
    + * *_early_ptr's are zeroed indicating that the static arrays are gone.
    + */
    +static void __init setup_per_cpu_maps(void)
    +{
    + int cpu;
    +
    + for_each_possible_cpu(cpu) {
    +#ifdef CONFIG_SMP
    + if (per_cpu_offset(cpu)) {
    +#endif
    + per_cpu(x86_cpu_to_apicid, cpu) =
    + x86_cpu_to_apicid_init[cpu];
    + per_cpu(x86_bios_cpu_apicid, cpu) =
    + x86_bios_cpu_apicid_init[cpu];
    +#ifdef CONFIG_NUMA
    + per_cpu(x86_cpu_to_node_map, cpu) =
    + x86_cpu_to_node_map_init[cpu];
    +#endif
    +#ifdef CONFIG_SMP
    + } else
    + printk(KERN_NOTICE "per_cpu_offset zero for cpu %d\n",
    + cpu);
    +#endif
    + }
    +
    + /* indicate the early static arrays will soon be gone */
    + x86_cpu_to_apicid_early_ptr = NULL;
    + x86_bios_cpu_apicid_early_ptr = NULL;
    +#ifdef CONFIG_NUMA
    + x86_cpu_to_node_map_early_ptr = NULL;
    +#endif
    +}
    +
    +#ifdef CONFIG_X86_32
    +/*
    + * Great future not-so-futuristic plan: make i386 and x86_64 do it
    + * the same way
    + */
    +unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
    +EXPORT_SYMBOL(__per_cpu_offset);
    +#endif
    +
    +/*
    + * Great future plan:
    + * Declare PDA itself and support (irqstack,tss,pgd) as per cpu data.
    + * Always point %gs to its beginning
    + */
    +void __init setup_per_cpu_areas(void)
    +{
    + int i;
    + unsigned long size;
    +
    +#ifdef CONFIG_HOTPLUG_CPU
    + prefill_possible_map();
    +#endif
    +
    + /* Copy section for each CPU (we discard the original) */
    + size = PERCPU_ENOUGH_ROOM;
    +
    + printk(KERN_INFO "PERCPU: Allocating %lu bytes of per cpu data\n",
    + size);
    + for_each_cpu_mask(i, cpu_possible_map) {
    + char *ptr;
    +#ifndef CONFIG_NEED_MULTIPLE_NODES
    + ptr = alloc_bootmem_pages(size);
    +#else
    + int node = early_cpu_to_node(i);
    + if (!node_online(node) || !NODE_DATA(node))
    + ptr = alloc_bootmem_pages(size);
    + else
    + ptr = alloc_bootmem_pages_node(NODE_DATA(node), size);
    +#endif
    + if (!ptr)
    + panic("Cannot allocate cpu data for CPU %d\n", i);
    +#ifdef CONFIG_X86_64
    + cpu_pda(i)->data_offset = ptr - __per_cpu_start;
    +#else
    + __per_cpu_offset[i] = ptr - __per_cpu_start;
    +#endif
    + memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
    + }
    +
    + /* setup percpu data maps early */
    + setup_per_cpu_maps();
    +}
    +
    +#endif
    diff --git a/arch/x86/kernel/setup64.c b/arch/x86/kernel/setup64.c
    index 143aa78..d4e4281 100644
    --- a/arch/x86/kernel/setup64.c
    +++ b/arch/x86/kernel/setup64.c
    @@ -86,83 +86,6 @@ static int __init nonx32_setup(char *str)
    }
    __setup("noexec32=", nonx32_setup);

    -/*
    - * Copy data used in early init routines from the initial arrays to the
    - * per cpu data areas. These arrays then become expendable and the
    - * *_early_ptr's are zeroed indicating that the static arrays are gone.
    - */
    -static void __init setup_per_cpu_maps(void)
    -{
    - int cpu;
    -
    - for_each_possible_cpu(cpu) {
    -#ifdef CONFIG_SMP
    - if (per_cpu_offset(cpu)) {
    -#endif
    - per_cpu(x86_cpu_to_apicid, cpu) =
    - x86_cpu_to_apicid_init[cpu];
    - per_cpu(x86_bios_cpu_apicid, cpu) =
    - x86_bios_cpu_apicid_init[cpu];
    -#ifdef CONFIG_NUMA
    - per_cpu(x86_cpu_to_node_map, cpu) =
    - x86_cpu_to_node_map_init[cpu];
    -#endif
    -#ifdef CONFIG_SMP
    - }
    - else
    - printk(KERN_NOTICE "per_cpu_offset zero for cpu %d\n",
    - cpu);
    -#endif
    - }
    -
    - /* indicate the early static arrays will soon be gone */
    - x86_cpu_to_apicid_early_ptr = NULL;
    - x86_bios_cpu_apicid_early_ptr = NULL;
    -#ifdef CONFIG_NUMA
    - x86_cpu_to_node_map_early_ptr = NULL;
    -#endif
    -}
    -
    -/*
    - * Great future plan:
    - * Declare PDA itself and support (irqstack,tss,pgd) as per cpu data.
    - * Always point %gs to its beginning
    - */
    -void __init setup_per_cpu_areas(void)
    -{
    - int i;
    - unsigned long size;
    -
    -#ifdef CONFIG_HOTPLUG_CPU
    - prefill_possible_map();
    -#endif
    -
    - /* Copy section for each CPU (we discard the original) */
    - size = PERCPU_ENOUGH_ROOM;
    -
    - printk(KERN_INFO "PERCPU: Allocating %lu bytes of per cpu data\n", size);
    - for_each_cpu_mask (i, cpu_possible_map) {
    - char *ptr;
    -#ifndef CONFIG_NEED_MULTIPLE_NODES
    - ptr = alloc_bootmem_pages(size);
    -#else
    - int node = early_cpu_to_node(i);
    -
    - if (!node_online(node) || !NODE_DATA(node))
    - ptr = alloc_bootmem_pages(size);
    - else
    - ptr = alloc_bootmem_pages_node(NODE_DATA(node), size);
    -#endif
    - if (!ptr)
    - panic("Cannot allocate cpu data for CPU %d\n", i);
    - cpu_pda(i)->data_offset = ptr - __per_cpu_start;
    - memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
    - }
    -
    - /* setup percpu data maps early */
    - setup_per_cpu_maps();
    -}
    -
    void pda_init(int cpu)
    {
    struct x8664_pda *pda = cpu_pda(cpu);
    diff --git a/arch/x86/kernel/smpboot_32.c b/arch/x86/kernel/smpboot_32.c
    index 92a5df6..bf5c9e9 100644
    --- a/arch/x86/kernel/smpboot_32.c
    +++ b/arch/x86/kernel/smpboot_32.c
    @@ -665,6 +665,7 @@ static int __cpuinit do_boot_cpu(int apicid, int cpu)
    unmap_cpu_to_logical_apicid(cpu);
    cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
    cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
    + cpu_clear(cpu, cpu_possible_map);
    cpucount--;
    } else {
    per_cpu(x86_cpu_to_apicid, cpu) = apicid;
    @@ -743,6 +744,7 @@ EXPORT_SYMBOL(xquad_portio);

    static void __init disable_smp(void)
    {
    + cpu_possible_map = cpumask_of_cpu(0);
    smpboot_clear_io_apic_irqs();
    phys_cpu_present_map = physid_mask_of_physid(0);
    map_cpu_to_logical_apicid();
    --
    1.5.0.6

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  6. [PATCH 11/79] [PATCH] always enable irqs when entering idle

    From: Glauber Costa

    This matches x86_64 behaviour, which is a superior one IMHO

    Signed-off-by: Glauber Costa
    ---
    arch/x86/kernel/process_32.c | 9 +++++++--
    1 files changed, 7 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
    index ec05fb7..08c41ed 100644
    --- a/arch/x86/kernel/process_32.c
    +++ b/arch/x86/kernel/process_32.c
    @@ -127,6 +127,7 @@ void default_idle(void)
    local_irq_enable();
    current_thread_info()->status |= TS_POLLING;
    } else {
    + local_irq_enable();
    /* loop is done by the caller */
    cpu_relax();
    }
    @@ -142,6 +143,7 @@ EXPORT_SYMBOL(default_idle);
    */
    static void poll_idle(void)
    {
    + local_irq_enable();
    cpu_relax();
    }

    @@ -248,8 +250,11 @@ void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
    __monitor((void *)&current_thread_info()->flags, 0, 0);
    smp_mb();
    if (!need_resched())
    - __mwait(ax, cx);
    - }
    + __sti_mwait(ax, cx);
    + else
    + local_irq_enable();
    + } else
    + local_irq_enable();
    }

    /* Default MONITOR/MWAIT with no hints, used for default C1 state */
    --
    1.5.0.6

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  7. Re: [PATCH 0/79] smpboot integration


    * Glauber de Oliveira Costa wrote:

    > Testing and bisectability:
    >
    > The end result was tested in all my hardware (which includes qemu ;-).
    > It does not mean it will boot _your_ hardware, but I did my best ;-)
    >
    > The tree at least compiles in more than 20 randconfigs (for each of
    > x86_64 and i386) For i386, each of the subarchitectures was compiled
    > at least once. (By compile, I obviously mean, every patch,
    > individually)


    very nice work! I'll pick it up - and i'm not too worried about
    breakages because at 80 patches granularity any problem should be
    identifiable in a very finegrained way.

    Ingo
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  8. Re: [PATCH 0/79] smpboot integration


    the small fix below was needed - it is possible to build ACPI on 32-bit
    with APIC support disabled. Otherwise it's looking good in my testing.

    Ingo

    -----------------
    Subject: x86: smp unify2 include mach apic h in smpboot 64 c and smpboot c fix
    From: Ingo Molnar
    Date: Wed Mar 19 19:25:58 CET 2008

    Signed-off-by: Ingo Molnar
    ---
    arch/x86/kernel/acpi/boot.c | 4 +++-
    1 file changed, 3 insertions(+), 1 deletion(-)

    Index: linux-x86.q/arch/x86/kernel/acpi/boot.c
    ================================================== =================
    --- linux-x86.q.orig/arch/x86/kernel/acpi/boot.c
    +++ linux-x86.q/arch/x86/kernel/acpi/boot.c
    @@ -40,7 +40,9 @@
    #include
    #include

    -#include
    +#ifdef CONFIG_X86_LOCAL_APIC
    +# include
    +#endif

    static int __initdata acpi_force = 0;

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  9. Re: [PATCH 0/79] smpboot integration

    On Wed, Mar 19, 2008 at 10:35 AM, Ingo Molnar wrote:
    >
    > * Glauber de Oliveira Costa wrote:
    >
    > > Testing and bisectability:
    > >
    > > The end result was tested in all my hardware (which includes qemu ;-).
    > > It does not mean it will boot _your_ hardware, but I did my best ;-)
    > >
    > > The tree at least compiles in more than 20 randconfigs (for each of
    > > x86_64 and i386) For i386, each of the subarchitectures was compiled
    > > at least once. (By compile, I obviously mean, every patch,
    > > individually)

    >
    > very nice work! I'll pick it up - and i'm not too worried about
    > breakages because at 80 patches granularity any problem should be
    > identifiable in a very finegrained way.
    >


    it broke 4 sockets quad core above with 64 bit

    Booting processor 11/15 ip 6000
    Initializing CPU#11
    masked ExtINT on CPU#11
    Calibrating delay using timer specific routine.. 4589.46 BogoMIPS (lpj=9178934)
    CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
    CPU: L2 Cache: 512K (64 bytes/line)
    CPU 11/f -> Node 2
    CPU: Physical Processor ID: 2
    CPU: Processor Core ID: 3
    CPU11: Quad-Core AMD Opteron(tm) Processor 8356 stepping 03
    checking TSC synchronization [CPU#0 -> CPU#11]: passed.
    Booting processor 12/16 ip 6000

    looks like local apic id up 4 bit is masked out. so can not start 0x10
    above any more.

    YH
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  10. Re: [PATCH 0/79] smpboot integration

    On Wed, Mar 19, 2008 at 7:18 PM, Yinghai Lu wrote:
    > On Wed, Mar 19, 2008 at 10:35 AM, Ingo Molnar wrote:
    > >
    > > * Glauber de Oliveira Costa wrote:
    > >
    > > > Testing and bisectability:
    > > >
    > > > The end result was tested in all my hardware (which includes qemu ;-).
    > > > It does not mean it will boot _your_ hardware, but I did my best ;-)
    > > >
    > > > The tree at least compiles in more than 20 randconfigs (for each of
    > > > x86_64 and i386) For i386, each of the subarchitectures was compiled
    > > > at least once. (By compile, I obviously mean, every patch,
    > > > individually)

    > >
    > > very nice work! I'll pick it up - and i'm not too worried about
    > > breakages because at 80 patches granularity any problem should be
    > > identifiable in a very finegrained way.
    > >

    >
    > it broke 4 sockets quad core above with 64 bit
    >
    > Booting processor 11/15 ip 6000
    > Initializing CPU#11
    > masked ExtINT on CPU#11
    > Calibrating delay using timer specific routine.. 4589.46 BogoMIPS (lpj=9178934)
    > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
    > CPU: L2 Cache: 512K (64 bytes/line)
    > CPU 11/f -> Node 2
    > CPU: Physical Processor ID: 2
    > CPU: Processor Core ID: 3
    > CPU11: Quad-Core AMD Opteron(tm) Processor 8356 stepping 03
    > checking TSC synchronization [CPU#0 -> CPU#11]: passed.
    > Booting processor 12/16 ip 6000
    >
    > looks like local apic id up 4 bit is masked out. so can not start 0x10
    > above any more.


    in wakeup_secondary_via_INIT
    before the patchsets
    64 bit code:

    /*
    * Send IPI
    */
    apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
    | APIC_DM_INIT);


    after patchset

    /* Boot on the stack */
    /* Kick the second */
    apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);

    So that is wrong! esp for system has ext apic id that is has 8 bits
    instead of 4 bits.

    YH
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  11. Re: [PATCH 0/79] smpboot integration

    On Wed, Mar 19, 2008 at 8:00 PM, Yinghai Lu wrote:
    >
    > On Wed, Mar 19, 2008 at 7:18 PM, Yinghai Lu wrote:
    > > On Wed, Mar 19, 2008 at 10:35 AM, Ingo Molnar wrote:
    > > >
    > > > * Glauber de Oliveira Costa wrote:
    > > >
    > > > > Testing and bisectability:
    > > > >
    > > > > The end result was tested in all my hardware (which includes qemu ;-).
    > > > > It does not mean it will boot _your_ hardware, but I did my best ;-)
    > > > >
    > > > > The tree at least compiles in more than 20 randconfigs (for each of
    > > > > x86_64 and i386) For i386, each of the subarchitectures was compiled
    > > > > at least once. (By compile, I obviously mean, every patch,
    > > > > individually)
    > > >
    > > > very nice work! I'll pick it up - and i'm not too worried about
    > > > breakages because at 80 patches granularity any problem should be
    > > > identifiable in a very finegrained way.
    > > >

    > >
    > > it broke 4 sockets quad core above with 64 bit
    > >
    > > Booting processor 11/15 ip 6000
    > > Initializing CPU#11
    > > masked ExtINT on CPU#11
    > > Calibrating delay using timer specific routine.. 4589.46 BogoMIPS (lpj=9178934)
    > > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
    > > CPU: L2 Cache: 512K (64 bytes/line)
    > > CPU 11/f -> Node 2
    > > CPU: Physical Processor ID: 2
    > > CPU: Processor Core ID: 3
    > > CPU11: Quad-Core AMD Opteron(tm) Processor 8356 stepping 03
    > > checking TSC synchronization [CPU#0 -> CPU#11]: passed.
    > > Booting processor 12/16 ip 6000
    > >
    > > looks like local apic id up 4 bit is masked out. so can not start 0x10
    > > above any more.

    >
    > in wakeup_secondary_via_INIT
    > before the patchsets
    > 64 bit code:
    >
    > /*
    > * Send IPI
    > */
    > apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
    > | APIC_DM_INIT);
    >
    >
    > after patchset
    >
    > /* Boot on the stack */
    > /* Kick the second */
    > apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
    >
    > So that is wrong! esp for system has ext apic id that is has 8 bits
    > instead of 4 bits.
    >


    it seems there is two wakeup_secondary_cpu. one for NMI and one INIT.

    but should have

    #define WAKE_SECONDARY_VIA_INIT

    for x86_64

    but after

    #ifdef CONFIG_X86_64
    #undef WAKE_SECONDARY_VIA_NMI
    #define WAKE_SECONDARY_VIA_INIT
    #endif

    it still doesn't work.

    YH
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  12. Re: [PATCH 0/79] smpboot integration

    Yinghai Lu wrote:
    > On Wed, Mar 19, 2008 at 8:00 PM, Yinghai Lu wrote:
    >> On Wed, Mar 19, 2008 at 7:18 PM, Yinghai Lu wrote:
    >> > On Wed, Mar 19, 2008 at 10:35 AM, Ingo Molnar wrote:
    >> > >
    >> > > * Glauber de Oliveira Costa wrote:
    >> > >
    >> > > > Testing and bisectability:
    >> > > >
    >> > > > The end result was tested in all my hardware (which includes qemu ;-).
    >> > > > It does not mean it will boot _your_ hardware, but I did my best ;-)
    >> > > >
    >> > > > The tree at least compiles in more than 20 randconfigs (for each of
    >> > > > x86_64 and i386) For i386, each of the subarchitectures was compiled
    >> > > > at least once. (By compile, I obviously mean, every patch,
    >> > > > individually)
    >> > >
    >> > > very nice work! I'll pick it up - and i'm not too worried about
    >> > > breakages because at 80 patches granularity any problem should be
    >> > > identifiable in a very finegrained way.
    >> > >
    >> >
    >> > it broke 4 sockets quad core above with 64 bit
    >> >
    >> > Booting processor 11/15 ip 6000
    >> > Initializing CPU#11
    >> > masked ExtINT on CPU#11
    >> > Calibrating delay using timer specific routine.. 4589.46 BogoMIPS (lpj=9178934)
    >> > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
    >> > CPU: L2 Cache: 512K (64 bytes/line)
    >> > CPU 11/f -> Node 2
    >> > CPU: Physical Processor ID: 2
    >> > CPU: Processor Core ID: 3
    >> > CPU11: Quad-Core AMD Opteron(tm) Processor 8356 stepping 03
    >> > checking TSC synchronization [CPU#0 -> CPU#11]: passed.
    >> > Booting processor 12/16 ip 6000
    >> >
    >> > looks like local apic id up 4 bit is masked out. so can not start 0x10
    >> > above any more.

    >>
    >> in wakeup_secondary_via_INIT
    >> before the patchsets
    >> 64 bit code:
    >>
    >> /*
    >> * Send IPI
    >> */
    >> apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
    >> | APIC_DM_INIT);
    >>
    >>
    >> after patchset
    >>
    >> /* Boot on the stack */
    >> /* Kick the second */
    >> apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
    >>
    >> So that is wrong! esp for system has ext apic id that is has 8 bits
    >> instead of 4 bits.
    >>

    >
    > it seems there is two wakeup_secondary_cpu. one for NMI and one INIT.
    >
    > but should have
    >
    > #define WAKE_SECONDARY_VIA_INIT
    >
    > for x86_64
    >
    > but after
    >
    > #ifdef CONFIG_X86_64
    > #undef WAKE_SECONDARY_VIA_NMI
    > #define WAKE_SECONDARY_VIA_INIT
    > #endif
    >
    > it still doesn't work.
    >
    > YH

    Thanks for the testing Yinghai. I'll take a deeper look as soon as I
    can. The two routines are provided, since i386 numa-q inits the startup
    sequence through NMIs. The _VIA_INIT is already defined in x86_64 in the
    mach-default/ headers.

    What happens exactly? Does it hang indefinitely ? Or just for a while?
    Also, can you provide the exact commit in which this problem start?
    (just to be sure)

    As a debugging aid, can you also define the Dprintks in the code? I've
    seen hangs before in which the processor was indeed executing its init
    sequence, (although it did not seem to), but was hanging in the
    calibrate loop.

    Thanks
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  13. Re: [PATCH 0/79] smpboot integration

    On Wed, Mar 19, 2008 at 9:40 PM, Glauber Costa wrote:
    >
    > Yinghai Lu wrote:
    > > On Wed, Mar 19, 2008 at 8:00 PM, Yinghai Lu wrote:
    > >> On Wed, Mar 19, 2008 at 7:18 PM, Yinghai Lu wrote:
    > >> > On Wed, Mar 19, 2008 at 10:35 AM, Ingo Molnar wrote:
    > >> > >
    > >> > > * Glauber de Oliveira Costa wrote:
    > >> > >
    > >> > > > Testing and bisectability:
    > >> > > >
    > >> > > > The end result was tested in all my hardware (which includes qemu ;-).
    > >> > > > It does not mean it will boot _your_ hardware, but I did my best ;-)
    > >> > > >
    > >> > > > The tree at least compiles in more than 20 randconfigs (for each of
    > >> > > > x86_64 and i386) For i386, each of the subarchitectures was compiled
    > >> > > > at least once. (By compile, I obviously mean, every patch,
    > >> > > > individually)
    > >> > >
    > >> > > very nice work! I'll pick it up - and i'm not too worried about
    > >> > > breakages because at 80 patches granularity any problem should be
    > >> > > identifiable in a very finegrained way.
    > >> > >
    > >> >
    > >> > it broke 4 sockets quad core above with 64 bit
    > >> >
    > >> > Booting processor 11/15 ip 6000
    > >> > Initializing CPU#11
    > >> > masked ExtINT on CPU#11
    > >> > Calibrating delay using timer specific routine.. 4589.46 BogoMIPS (lpj=9178934)
    > >> > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
    > >> > CPU: L2 Cache: 512K (64 bytes/line)
    > >> > CPU 11/f -> Node 2
    > >> > CPU: Physical Processor ID: 2
    > >> > CPU: Processor Core ID: 3
    > >> > CPU11: Quad-Core AMD Opteron(tm) Processor 8356 stepping 03
    > >> > checking TSC synchronization [CPU#0 -> CPU#11]: passed.
    > >> > Booting processor 12/16 ip 6000
    > >> >
    > >> > looks like local apic id up 4 bit is masked out. so can not start 0x10
    > >> > above any more.
    > >>
    > >> in wakeup_secondary_via_INIT
    > >> before the patchsets
    > >> 64 bit code:
    > >>
    > >> /*
    > >> * Send IPI
    > >> */
    > >> apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
    > >> | APIC_DM_INIT);
    > >>
    > >>
    > >> after patchset
    > >>
    > >> /* Boot on the stack */
    > >> /* Kick the second */
    > >> apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
    > >>
    > >> So that is wrong! esp for system has ext apic id that is has 8 bits
    > >> instead of 4 bits.
    > >>

    > >
    > > it seems there is two wakeup_secondary_cpu. one for NMI and one INIT.
    > >
    > > but should have
    > >
    > > #define WAKE_SECONDARY_VIA_INIT
    > >
    > > for x86_64
    > >
    > > but after
    > >
    > > #ifdef CONFIG_X86_64
    > > #undef WAKE_SECONDARY_VIA_NMI
    > > #define WAKE_SECONDARY_VIA_INIT
    > > #endif
    > >
    > > it still doesn't work.
    > >
    > > YH

    > Thanks for the testing Yinghai. I'll take a deeper look as soon as I
    > can. The two routines are provided, since i386 numa-q inits the startup
    > sequence through NMIs. The _VIA_INIT is already defined in x86_64 in the
    > mach-default/ headers.
    >
    > What happens exactly? Does it hang indefinitely ? Or just for a while?
    > Also, can you provide the exact commit in which this problem start?
    > (just to be sure)


    hang indefinitely.

    maybe some apic code merge problem...

    YH
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  14. Re: [PATCH 58/79] [PATCH] include mach_apic.h in smpboot_64.c and smpboot.c

    On Wed, Mar 19, 2008 at 10:25 AM, Glauber de Oliveira Costa
    wrote:
    > From: Glauber Costa
    >
    > After the inclusion, a lot of files needs fixing for conflicts,
    > some of them in the headers themselves, to accomodate for both
    > i386 and x86_64 versions.
    >
    > Signed-off-by: Glauber Costa
    > ---
    > arch/x86/kernel/acpi/boot.c | 2 ++
    > arch/x86/kernel/mpparse_64.c | 2 ++
    > arch/x86/kernel/smpboot.c | 2 ++
    > arch/x86/kernel/smpboot_64.c | 1 +
    > arch/x86/vdso/Makefile | 2 +-
    > include/asm-x86/apic.h | 1 -
    > include/asm-x86/apicdef.h | 6 ------
    > include/asm-x86/mach-default/mach_apic.h | 11 +++++++++++
    > include/asm-x86/mach-default/mach_apicdef.h | 5 +++++
    > include/asm-x86/smp_64.h | 9 +--------
    > 10 files changed, 25 insertions(+), 16 deletions(-)


    please don't.

    before this patch
    include/asm-x86/mach_apic.h is only for x86_64 only
    include/asm-x86/mach-default/mach_apic.h is for i386 only.

    and both have __ASM_MACH_APIC_H defined.

    may need another name?

    YH
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  15. Re: [PATCH 45/79] [PATCH] fix apic acking of irqs

    On Wed, 19 Mar 2008, Glauber de Oliveira Costa wrote:

    > EOI is a write-only register. Using write around will have the effect
    > of reading it, which will make all subsequent reads of the ESR register
    > to return an error code. It was unnotices for quite a while because main sources
    > of reading the ESR register where done prior to apic interrupt enabling.


    Are you sure this actually triggers for APIC chips affected by the
    erratum in question? And please note that for them the effect of two
    consecutive writes will be much more disastrous than setting a bit in the
    ESR register.

    Maciej
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  16. Re: [PATCH 58/79] [PATCH] include mach_apic.h in smpboot_64.c and smpboot.c

    Yinghai Lu wrote:
    > On Wed, Mar 19, 2008 at 10:25 AM, Glauber de Oliveira Costa
    > wrote:
    >> From: Glauber Costa
    >>
    >> After the inclusion, a lot of files needs fixing for conflicts,
    >> some of them in the headers themselves, to accomodate for both
    >> i386 and x86_64 versions.
    >>
    >> Signed-off-by: Glauber Costa
    >> ---
    >> arch/x86/kernel/acpi/boot.c | 2 ++
    >> arch/x86/kernel/mpparse_64.c | 2 ++
    >> arch/x86/kernel/smpboot.c | 2 ++
    >> arch/x86/kernel/smpboot_64.c | 1 +
    >> arch/x86/vdso/Makefile | 2 +-
    >> include/asm-x86/apic.h | 1 -
    >> include/asm-x86/apicdef.h | 6 ------
    >> include/asm-x86/mach-default/mach_apic.h | 11 +++++++++++
    >> include/asm-x86/mach-default/mach_apicdef.h | 5 +++++
    >> include/asm-x86/smp_64.h | 9 +--------
    >> 10 files changed, 25 insertions(+), 16 deletions(-)

    >
    > please don't.
    >
    > before this patch
    > include/asm-x86/mach_apic.h is only for x86_64 only
    > include/asm-x86/mach-default/mach_apic.h is for i386 only.
    >
    > and both have __ASM_MACH_APIC_H defined.
    >
    > may need another name?
    >
    > YH

    Another name is possible, but I'd prefer to get rid of the
    asm-x86/mach_apic.h. The goal here is to have things integrated, so
    unless really necessary, this is prefered.

    Is this related to your problem anyhow? (just in curiosity)

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  17. Re: [PATCH 45/79] [PATCH] fix apic acking of irqs

    Maciej W. Rozycki wrote:
    > On Wed, 19 Mar 2008, Glauber de Oliveira Costa wrote:
    >
    >> EOI is a write-only register. Using write around will have the effect
    >> of reading it, which will make all subsequent reads of the ESR register
    >> to return an error code. It was unnotices for quite a while because main sources
    >> of reading the ESR register where done prior to apic interrupt enabling.

    >
    > Are you sure this actually triggers for APIC chips affected by the
    > erratum in question? And please note that for them the effect of two
    > consecutive writes will be much more disastrous than setting a bit in the
    > ESR register.
    >
    > Maciej


    I'm not _sure_, but I can't find anything in the errata list that states
    otherwise. It would be great that anyone has such a system to test it.
    But with the current conditions, it will break bootup code. In case it
    is really a problem, we'd need to make a special case for that.
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  18. Re: [PATCH 58/79] [PATCH] include mach_apic.h in smpboot_64.c and smpboot.c

    On Thu, Mar 20, 2008 at 7:25 AM, Glauber Costa wrote:
    >
    > Yinghai Lu wrote:
    > >> 10 files changed, 25 insertions(+), 16 deletions(-)

    > >
    > > please don't.
    > >
    > > before this patch
    > > include/asm-x86/mach_apic.h is only for x86_64 only
    > > include/asm-x86/mach-default/mach_apic.h is for i386 only.
    > >
    > > and both have __ASM_MACH_APIC_H defined.
    > >
    > > may need another name?
    > >
    > > YH

    > Another name is possible, but I'd prefer to get rid of the
    > asm-x86/mach_apic.h. The goal here is to have things integrated, so
    > unless really necessary, this is prefered.
    >
    > Is this related to your problem anyhow? (just in curiosity)


    No

    YH
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  19. Re: [PATCH 45/79] [PATCH] fix apic acking of irqs

    On Thu, 20 Mar 2008, Glauber Costa wrote:

    > > Are you sure this actually triggers for APIC chips affected by the erratum
    > > in question? And please note that for them the effect of two consecutive
    > > writes will be much more disastrous than setting a bit in the ESR register.

    >
    > I'm not _sure_, but I can't find anything in the errata list that states
    > otherwise. It would be great that anyone has such a system to test it. But
    > with the current conditions, it will break bootup code. In case it is really a
    > problem, we'd need to make a special case for that.


    I have dug out the relevant erratum -- it is the 11AP one as referred to
    from arch/x86/kernel/smp_32.c and the text even mentions the EOI register
    explicitly:

    "This problem affects systems that use HOLD/HLDA or BOFF# and enable the
    local APIC of the CPU. If the second APIC write cycle is an EOI (End of
    Interrupt) cycle, the CPU will stop servicing subsequent interrupts of
    equal or less priority. This may cause the system to hang. If the second
    APIC write cycle is not an EOI, the failure mode would depend on the
    particular APIC register that is not updated correctly."

    But on this occasion I took the opportunity to refresh my memory on the
    ESR register and there is apparently no bit there, at least up to
    Pentium4, that would signify an error resulting from an incorrect access
    type -- only accesses to invalid register indices are marked as errors.

    Which bit of the ESR can you see set as a result of using an RMW cycle to
    the EOI register and with what kind of CPU/APIC? And why wouldn't it have
    affected older kernels? -- the error interrupt has been kept enabled by
    Linux for ages and writes to the EOI register are frequent enough it would
    be hard to miss the resulting flood of errors. Hmm...

    Maciej
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  20. Re: [PATCH 0/79] smpboot integration


    * Yinghai Lu wrote:

    > attached patch fix that.


    thanks Yinghai, applied.

    Ingo
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