[PATCH 1/8] x86_64: check MSR to get MMCONFIG for AMD Family 10h Opteron v3 - Kernel

This is a discussion on [PATCH 1/8] x86_64: check MSR to get MMCONFIG for AMD Family 10h Opteron v3 - Kernel ; From: Yinghai Lu so even booting kernel with acpi=off or even MCFG is not there, we still can use MMCONFIG. Signed-off-by: Yinghai Lu Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Andi Kleen Cc: Greg KH Cc: "H. Peter Anvin" Signed-off-by: ...

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Thread: [PATCH 1/8] x86_64: check MSR to get MMCONFIG for AMD Family 10h Opteron v3

  1. [PATCH 1/8] x86_64: check MSR to get MMCONFIG for AMD Family 10h Opteron v3


    From: Yinghai Lu

    so even booting kernel with acpi=off or even MCFG is not there, we still can
    use MMCONFIG.

    Signed-off-by: Yinghai Lu
    Cc: Thomas Gleixner
    Cc: Ingo Molnar
    Cc: Andi Kleen
    Cc: Greg KH
    Cc: "H. Peter Anvin"
    Signed-off-by: Andrew Morton
    ---

    Index: linux-2.6/arch/x86/pci/mmconfig-shared.c
    ================================================== =================
    --- linux-2.6.orig/arch/x86/pci/mmconfig-shared.c
    +++ linux-2.6/arch/x86/pci/mmconfig-shared.c
    @@ -100,33 +100,88 @@ static const char __init *pci_mmcfg_inte
    return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
    }

    +static const char __init *pci_mmcfg_amd_fam10h(void)
    +{
    + u32 low, high, address;
    + u64 base, msr;
    + int i;
    + unsigned segnbits = 0, busnbits;
    +
    + address = MSR_FAM10H_MMIO_CONF_BASE;
    + if (rdmsr_safe(address, &low, &high))
    + return NULL;
    +
    + msr = high;
    + msr <<= 32;
    + msr |= low;
    +
    + /* mmconfig is not enable */
    + if (!(msr & FAM10H_MMIO_CONF_ENABLE))
    + return NULL;
    +
    + base = msr & (FAM10H_MMIO_CONF_BASE_MASK< +
    + busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
    + FAM10H_MMIO_CONF_BUSRANGE_MASK;
    + if (busnbits > 8) {
    + segnbits = busnbits - 8;
    + busnbits = 8;
    + }
    +
    + pci_mmcfg_config_num = (1 << segnbits);
    + pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
    + pci_mmcfg_config_num, GFP_KERNEL);
    + if (!pci_mmcfg_config)
    + return NULL;
    +
    + for (i = 0; i < (1 << segnbits); i++) {
    + pci_mmcfg_config[i].address = base + (1<<28) * i;
    + pci_mmcfg_config[i].pci_segment = i;
    + pci_mmcfg_config[i].start_bus_number = 0;
    + pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
    + }
    +
    + return "AMD Family 10h NB";
    +}
    +
    struct pci_mmcfg_hostbridge_probe {
    + u32 bus;
    + u32 devfn;
    u32 vendor;
    u32 device;
    const char *(*probe)(void);
    };

    static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
    - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
    - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
    + { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
    + PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
    + { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
    + PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
    + { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
    + 0x1200, pci_mmcfg_amd_fam10h },
    + { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
    + 0x1200, pci_mmcfg_amd_fam10h },
    };

    static int __init pci_mmcfg_check_hostbridge(void)
    {
    u32 l;
    + u32 bus, devfn;
    u16 vendor, device;
    int i;
    const char *name;

    - pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0, 4, &l);
    - vendor = l & 0xffff;
    - device = (l >> 16) & 0xffff;
    -
    pci_mmcfg_config_num = 0;
    pci_mmcfg_config = NULL;
    name = NULL;

    for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
    + bus = pci_mmcfg_probes[i].bus;
    + devfn = pci_mmcfg_probes[i].devfn;
    + pci_direct_conf1.read(0, bus, devfn, 0, 4, &l);
    + vendor = l & 0xffff;
    + device = (l >> 16) & 0xffff;
    +
    if (pci_mmcfg_probes[i].vendor == vendor &&
    pci_mmcfg_probes[i].device == device)
    name = pci_mmcfg_probes[i].probe();
    --
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  2. [PATCH] x86: skip it if Fam 10h only handle bus 0


    need to apply after
    x86_64: check MSR to get MMCONFIG for AMD Family 10h Opteron v3

    some BIOS only let AMD fam 10h handle bus0, and nvidia mcp55/ck804
    to handle other buses. at that case MCFG will cover all over them.

    this patch will skip it so to use MCFG later.

    Signed-off-by: Yinghai Lu

    Index: linux-2.6/arch/x86/pci/mmconfig-shared.c
    ================================================== =================
    --- linux-2.6.orig/arch/x86/pci/mmconfig-shared.c
    +++ linux-2.6/arch/x86/pci/mmconfig-shared.c
    @@ -123,6 +123,14 @@ static const char __init *pci_mmcfg_amd_

    busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
    FAM10H_MMIO_CONF_BUSRANGE_MASK;
    +
    + /*
    + * only handle bus 0 ?
    + * need to skip it
    + */
    + if (!busnbits)
    + return NULL;
    +
    if (busnbits > 8) {
    segnbits = busnbits - 8;
    busnbits = 8;
    --
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