size of atomic memory read/write

Hello all,

I don't know much about HP machine's architecture. Does anyone know if HP's
SMP has weakly or strongly consistent memory? Also,if the data is aligned,
at what size does it guarantee atomic read/write to the data?

Thanks!

-DYZ

DYZ <spambegone@optonline.net> wrote:[color=blue]
> I don't know much about HP machine's architecture. Does anyone know
> if HP's SMP has weakly or strongly consistent memory? Also,if the
> data is aligned, at what size does it guarantee atomic read/write to
> the data?[/color]

I'm not sure if the answer is different, but are you talking about
PA-RISC or Itanium? HP-UX runs on both.

rick jones
--
No need to believe in either side, or any side. There is no cause.
There's only yourself. The belief is in your own precision. - Jobert
these opinions are mine, all mine; HP might not want them anyway... :)
feel free to post, OR email to rick.jones2 in hp.com but NOT BOTH...

Rick Jones <rick.jones2@hp.com> wrote in news:IaL6h.2513$OF4.960
@news.cpqcorp.net:
[color=blue]
> DYZ <spambegone@optonline.net> wrote:[color=green]
>> I don't know much about HP machine's architecture. Does anyone know
>> if HP's SMP has weakly or strongly consistent memory? Also,if the
>> data is aligned, at what size does it guarantee atomic read/write to
>> the data?[/color]
>
> I'm not sure if the answer is different, but are you talking about
> PA-RISC or Itanium? HP-UX runs on both.
>
> rick jones[/color]

Let's first assume this is on PA-RISC, but I'm more than happy to know the
answer for both. Thanks again!

DYZ

DYZ <spambegone@optonline.net> wrote:[color=blue]
> Rick Jones <rick.jones2@hp.com> wrote in news:IaL6h.2513$OF4.960
> @news.cpqcorp.net:[/color]
[color=blue][color=green]
>> DYZ <spambegone@optonline.net> wrote:[color=darkred]
>>> I don't know much about HP machine's architecture. Does anyone know
>>> if HP's SMP has weakly or strongly consistent memory? Also,if the
>>> data is aligned, at what size does it guarantee atomic read/write to
>>> the data?[/color]
>>
>> I'm not sure if the answer is different, but are you talking about
>> PA-RISC or Itanium? HP-UX runs on both.
>>
>> rick jones[/color][/color]
[color=blue]
> Let's first assume this is on PA-RISC, but I'm more than happy to
> know the answer for both. Thanks again![/color]

Well at the considerable risk of being wrong :) I believe that
four-byte reads/writes on a four-byte bondary are "atomic" on PA-RISC.
It is _possible_ that is 8 byte (64-bit) on later PA-RISC.

Some of the docs at [url]www.parisc-linux.org[/url] may have something to say on
the topic if nothing in docs.hp.com does, nor web searching.

rick jones
--
web2.0 n, the dot.com reunion tour...
these opinions are mine, all mine; HP might not want them anyway... :)
feel free to post, OR email to rick.jones2 in hp.com but NOT BOTH...

Thanks for the pointer to the docs. It's very helpful. Basically the
load and store instructions are atomic. So unless the compiler uses
multiple STORE BYTE instructions for the store of a single word or
doubleword (cannot imagine it'll do that), it is atomic to read/write
a word or double word.

-DYZ

Rick Jones <rick.jones2@hp.com> wrote in
news:VpN6h.2529$JM4.929@news.cpqcorp.net:
[color=blue]
> DYZ <spambegone@optonline.net> wrote:[color=green]
>> Rick Jones <rick.jones2@hp.com> wrote in news:IaL6h.2513$OF4.960
>> @news.cpqcorp.net:[/color]
>[color=green][color=darkred]
>>> DYZ <spambegone@optonline.net> wrote:
>>>> I don't know much about HP machine's architecture. Does anyone know
>>>> if HP's SMP has weakly or strongly consistent memory? Also,if the
>>>> data is aligned, at what size does it guarantee atomic read/write
>>>> to the data?
>>>
>>> I'm not sure if the answer is different, but are you talking about
>>> PA-RISC or Itanium? HP-UX runs on both.
>>>
>>> rick jones[/color][/color]
>[color=green]
>> Let's first assume this is on PA-RISC, but I'm more than happy to
>> know the answer for both. Thanks again![/color]
>
> Well at the considerable risk of being wrong :) I believe that
> four-byte reads/writes on a four-byte bondary are "atomic" on PA-RISC.
> It is _possible_ that is 8 byte (64-bit) on later PA-RISC.
>
> Some of the docs at [url]www.parisc-linux.org[/url] may have something to say on
> the topic if nothing in docs.hp.com does, nor web searching.
>
> rick jones[/color]

DYZ <spambegone@optonline.net> wrote:[color=blue]
> Thanks for the pointer to the docs. It's very helpful. Basically the
> load and store instructions are atomic. So unless the compiler uses
> multiple STORE BYTE instructions for the store of a single word or
> doubleword (cannot imagine it'll do that)[/color]

If you ask it to pack things or tell it to support unaligned stuff it
will :)

rick jones
--
The glass is neither half-empty nor half-full. The glass has a leak.
The real question is "Can it be patched?"
these opinions are mine, all mine; HP might not want them anyway... :)
feel free to post, OR email to rick.jones2 in hp.com but NOT BOTH...