endianess of the CPU Architecture - Hardware

This is a discussion on endianess of the CPU Architecture - Hardware ; Hi Everyone, I know that Big Endian is to have the big end first, in the sense 1234 stored as 12 34 first byte second byte and little endian would be 34 12 first byte second byte I hope its ...

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Thread: endianess of the CPU Architecture

  1. endianess of the CPU Architecture

    Hi Everyone,

    I know that Big Endian is to have the big end first, in the sense

    1234 stored as

    12 34
    first byte second byte

    and little endian would be

    34 12
    first byte second byte

    I hope its correct, then is it correct that many processors today are
    of big endian in nature including Intel ones?


  2. Re: endianess of the CPU Architecture

    sam_cit@yahoo.co.in wrote:
    > Hi Everyone,
    >
    > I know that Big Endian is to have the big end first, in the sense
    >
    > 1234 stored as
    >
    > 12 34
    > first byte second byte
    >
    > and little endian would be
    >
    > 34 12
    > first byte second byte
    >
    > I hope its correct, then is it correct that many processors today are
    > of big endian in nature including Intel ones?
    >


    No Intel processors are little endian.
    0x1234 is stored in memory as 34 (1st byte - lower address) and 12 (2nd
    byte - higher address) but when it is read in a processor register it
    results as 0x1234.

    Ciao
    Giovanni
    --
    A computer is like an air conditioner,
    it stops working when you open Windows.
    Registered Linux user #337974 < http://giovanni.homelinux.net/ >

  3. Re: endianess of the CPU Architecture

    On Monday 15 January 2007 10:46, sam_cit@yahoo.co.in wrote:

    > I know that Big Endian is to have the big end first, in the sense
    >
    > 1234 stored as
    >
    > 12 34
    > first byte second byte
    >
    > and little endian would be
    >
    > 34 12
    > first byte second byte
    >
    > I hope its correct, then is it correct that many processors today are
    > of big endian in nature including Intel ones?


    Try this document: http://www.cs.umass.edu/~verts/cs32/endian.html



    --
    Research is what I'm doing, when I don't know what I'm doing.
    (von Braun)


  4. Re: endianess of the CPU Architecture

    Giovanni wrote:

    > sam_cit@yahoo.co.in wrote:
    >> Hi Everyone,
    >>
    >> I know that Big Endian is to have the big end first, in the sense
    >>
    >> 1234 stored as
    >>
    >> 12 34
    >> first byte second byte
    >>
    >> and little endian would be
    >>
    >> 34 12
    >> first byte second byte
    >>
    >> I hope its correct, then is it correct that many processors today are
    >> of big endian in nature including Intel ones?
    >>

    >
    > No Intel processors are little endian.
    > 0x1234 is stored in memory as 34 (1st byte - lower address) and 12 (2nd
    > byte - higher address) but when it is read in a processor register it
    > results as 0x1234.
    >
    > Ciao
    > Giovanni


    That is not even enough to cover the territory. I have seen pin control of
    endian, software control of endian, chips that could change on the fly by
    instruction with specific endian properties. Motorola 68K and coldfire are
    big endian. Most Mips are pin and software switchable. I think SPARC is
    big endian. HP PArisc is mixed endian (endian is controllable in some
    instructions). And there are many architectures where i just don't know,
    e.g. SH3, AVR, acorn, PIC, transputer.

    --
    JosephKK
    Gegen dummheit kampfen die Gotter Selbst, vergebens.**
    --Schiller

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