Does memory CL timing change when Mhz drops for compatibility? - Hardware

This is a discussion on Does memory CL timing change when Mhz drops for compatibility? - Hardware ; I just put in a pair of Ballistix DDR PC3200 CL2 in my Dell Optiplex GX270 (with 800 Mhz FSB) and the BIOS says its running them at 333 Mhz. I've since concluded that this machine can only run PC3200 ...

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Thread: Does memory CL timing change when Mhz drops for compatibility?

  1. Does memory CL timing change when Mhz drops for compatibility?

    I just put in a pair of Ballistix DDR PC3200 CL2 in my Dell Optiplex
    GX270 (with 800 Mhz FSB) and the BIOS says its running them at 333 Mhz.
    I've since concluded that this machine can only run PC3200 at CL3 but
    what I want to know is what CL is it running at 333Mhz? This machine
    originally had a pair of 333Mhz CL2.5 and that was my first guess as to
    what it was running the PC3200 at but when I put in all four cards then
    it drops to 266Mhz. How can I see what the CL timing is for each of
    these configurations?

  2. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Oct 8, 4:04 am, Mike wrote:
    > I just put in a pair of Ballistix DDR PC3200 CL2 in my Dell Optiplex
    > GX270 (with 800 Mhz FSB) and the BIOS says its running them at 333 Mhz.
    > I've since concluded that this machine can only run PC3200 at CL3 but
    > what I want to know is what CL is it running at 333Mhz? This machine
    > originally had a pair of 333Mhz CL2.5 and that was my first guess as to
    > what it was running the PC3200 at but when I put in all four cards then
    > it drops to 266Mhz. How can I see what the CL timing is for each of
    > these configurations?


    Usually RAM dimms can operate at a lower bus speed than its rated
    value. If you mix dimms with different ratings, what will happen is
    that the lowest common denominator speed is selected. So your RAM
    will run at what the slowest dimm can handle.


  3. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Sun, 07 Oct 2007 18:04:04 GMT, Mike wrote:


    >I just put in a pair of Ballistix DDR PC3200 CL2 in my Dell Optiplex
    >GX270 (with 800 Mhz FSB) and the BIOS says its running them at 333 Mhz.
    >I've since concluded that this machine can only run PC3200 at CL3 but
    >what I want to know is what CL is it running at 333Mhz? This machine
    >originally had a pair of 333Mhz CL2.5 and that was my first guess as to
    >what it was running the PC3200 at but when I put in all four cards then
    >it drops to 266Mhz. How can I see what the CL timing is for each of
    >these configurations?


    CL refers to wait states. It has nothing to do with clock speed.

    There's a small chip (I2C interface?) on the memory module that is supposed
    to contain timing information. You shouldn't mix memory modules with
    different timing and some chipsets/BIOS will do better than others at
    handling the timing issue.

    You should be able to view the CL timing in the memory page of your BIOS.
    Usually there's one setting for the entire system. I've never seen a BIOS
    bright enough to have separate timing for each bank of memory.

  4. Re: Does memory CL timing change when Mhz drops for compatibility?

    Hello,

    AZ Nomad a écrit :
    >
    > CL refers to wait states. It has nothing to do with clock speed.


    Yes and no. On DRAM, CAS latency is fundamentally a continuous time,
    expressed in nanoseconds. As such, it is independent from the clock
    speed. But when converted to a dimensionless number of wait states i.e.
    a clock cycle count, by multiplying it with the clock frequency, the
    result depends on the clock speed.

    Take for example the Hyundai HY57V658020BTC-75 SDRAM chip rated for 133
    MHz clock speed (7.5 ns clock cycle time). When operating at 133 MHz the
    minimum CAS latency is 3 clock cycles but at 100 MHz and below it is 2
    clock cycles.

    3 / (133 MHz) = 22.5 ns
    2 / (100 MHz) = 20 ns

    So you can see that the underlying CAS latency time is ~ 20 ns.

  5. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Mon, 08 Oct 2007 10:30:33 +0200, Pascal Hambourg wrote:


    >Hello,


    >AZ Nomad a écrit :
    >>
    >> CL refers to wait states. It has nothing to do with clock speed.


    >Yes and no. On DRAM, CAS latency is fundamentally a continuous time,
    >expressed in nanoseconds. As such, it is independent from the clock
    >speed. But when converted to a dimensionless number of wait states i.e.
    >a clock cycle count, by multiplying it with the clock frequency, the
    >result depends on the clock speed.


    >Take for example the Hyundai HY57V658020BTC-75 SDRAM chip rated for 133
    >MHz clock speed (7.5 ns clock cycle time). When operating at 133 MHz the
    >minimum CAS latency is 3 clock cycles but at 100 MHz and below it is 2
    >clock cycles.


    >3 / (133 MHz) = 22.5 ns
    >2 / (100 MHz) = 20 ns


    >So you can see that the underlying CAS latency time is ~ 20 ns.


    Yes, but if you compare a PC3200 CL3 stick and a PC3200 CL2 stick, the
    difference is in the # of wait states. I wouldn't recomend running
    either at any clock other than 400mhz. Run it too slow and the cells
    won't be refreshed often enough; run it too fast and its access time will
    be too slow. I supposed you could run it a little out of spec like 333mhz
    with a fewer wait state. On a good day it might get refreshed often enough.

  6. Re: Does memory CL timing change when Mhz drops for compatibility?

    AZ Nomad a écrit :
    >
    >>Take for example the Hyundai HY57V658020BTC-75 SDRAM chip rated for 133
    >>MHz clock speed (7.5 ns clock cycle time). When operating at 133 MHz the
    >>minimum CAS latency is 3 clock cycles but at 100 MHz and below it is 2
    >>clock cycles.

    >
    > Yes, but if you compare a PC3200 CL3 stick and a PC3200 CL2 stick, the
    > difference is in the # of wait states.


    Sure. But it was not my point. My point is that you can use a lower CAS
    latency cycle count when the clocks runs at a lower speed.

    > I wouldn't recomend running
    > either at any clock other than 400mhz. Run it too slow and the cells
    > won't be refreshed often enough;


    Don't worry about that, the minimum clock speed is much lower that
    actual operating speeds. For instance the minimum clock frequency of the
    SDRAM chip I mentionned is 1 MHz.

    > run it too fast and its access time will be too slow.


    It is not only an access time issue, but that's the idea.

    > I supposed you could run it a little out of spec like 333mhz
    > with a fewer wait state.


    Yes.

  7. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Mon, 08 Oct 2007 20:48:36 +0200, Pascal Hambourg wrote:


    >AZ Nomad a écrit :
    >>
    >>>Take for example the Hyundai HY57V658020BTC-75 SDRAM chip rated for 133
    >>>MHz clock speed (7.5 ns clock cycle time). When operating at 133 MHz the
    >>>minimum CAS latency is 3 clock cycles but at 100 MHz and below it is 2
    >>>clock cycles.

    >>
    >> Yes, but if you compare a PC3200 CL3 stick and a PC3200 CL2 stick, the
    >> difference is in the # of wait states.


    >Sure. But it was not my point. My point is that you can use a lower CAS
    >latency cycle count when the clocks runs at a lower speed.


    >> I wouldn't recomend running
    >> either at any clock other than 400mhz. Run it too slow and the cells
    >> won't be refreshed often enough;


    >Don't worry about that, the minimum clock speed is much lower that
    >actual operating speeds. For instance the minimum clock frequency of the
    >SDRAM chip I mentionned is 1 MHz.


    That isn't the refresh period. That ram will fail if you run it on a
    66mhz motherboard.

  8. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Mon, 08 Oct 2007 10:30:33 +0200, Pascal Hambourg wrote:

    > Hello,
    >
    > AZ Nomad a écrit :
    >>
    >> CL refers to wait states. It has nothing to do with clock speed.

    >
    > Yes and no. On DRAM, CAS latency is fundamentally a continuous time,
    > expressed in nanoseconds. As such, it is independent from the clock
    > speed. But when converted to a dimensionless number of wait states i.e.
    > a clock cycle count, by multiplying it with the clock frequency, the
    > result depends on the clock speed.
    >
    > Take for example the Hyundai HY57V658020BTC-75 SDRAM chip rated for 133
    > MHz clock speed (7.5 ns clock cycle time). When operating at 133 MHz the
    > minimum CAS latency is 3 clock cycles but at 100 MHz and below it is 2
    > clock cycles.
    >
    > 3 / (133 MHz) = 22.5 ns
    > 2 / (100 MHz) = 20 ns
    >
    > So you can see that the underlying CAS latency time is ~ 20 ns.


    That is the type of calculation I was looking at that equates 333Mhz
    CL2.5 with 400Mhz CL3 (7.5 ns). So when I run the PC3200 (by itself) and
    it drops down to 333 Mhz I really don't know what the speed is if CL
    changes because it could be any of these:

    3/333 = 9ns
    2.5/333 = 7.5ns
    2/333 = 6.ns

    I'd like to think it's CL2 at 333Mhz which would be slightly better than
    400Mhz at CL2.5 (6ns vs 6.2ns). I'm still trying to understand exactly
    what the CL number means, I thought it was the number of clock cycles
    such that doubling the mhz or halving the CL is the same.


  9. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Mon, 08 Oct 2007 06:18:05 +0000, AZ Nomad wrote:

    > On Sun, 07 Oct 2007 18:04:04 GMT, Mike
    > wrote:
    >
    >
    >>I just put in a pair of Ballistix DDR PC3200 CL2 in my Dell Optiplex
    >>GX270 (with 800 Mhz FSB) and the BIOS says its running them at 333 Mhz.
    >>I've since concluded that this machine can only run PC3200 at CL3 but
    >>what I want to know is what CL is it running at 333Mhz? This machine
    >>originally had a pair of 333Mhz CL2.5 and that was my first guess as to
    >>what it was running the PC3200 at but when I put in all four cards then
    >>it drops to 266Mhz. How can I see what the CL timing is for each of
    >>these configurations?

    >
    > CL refers to wait states. It has nothing to do with clock speed.
    >
    > There's a small chip (I2C interface?) on the memory module that is
    > supposed to contain timing information. You shouldn't mix memory
    > modules with different timing and some chipsets/BIOS will do better than
    > others at handling the timing issue.
    >
    > You should be able to view the CL timing in the memory page of your
    > BIOS. Usually there's one setting for the entire system. I've never
    > seen a BIOS bright enough to have separate timing for each bank of
    > memory.


    I think this Dell BIOS is pretty lame in this regard, I don't see
    anything other than "system memory speed" and "bus speed" (which is under
    cpu infomration and is the FSB I believe).

    I was thinking perhaps the CL number could be found in some operating
    system file while the system is running? I did not mix memory modules in
    the first case which was a matched pair (for dual-channel) of PC3200, I
    only mentioned the second case because i thought the additional info
    might help but probably just confused the matter.

  10. Re: Does memory CL timing change when Mhz drops for compatibility?

    Mike writes:
    >I'm still trying to understand exactly
    >what the CL number means, I thought it was the number of clock cycles
    >such that doubling the mhz or halving the CL is the same.


    There's a series on memory on lwn.net. The first part explains CL and
    other latencies.

    - anton
    --
    M. Anton Ertl Some things have to be seen to be believed
    anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen
    http://www.complang.tuwien.ac.at/anton/home.html

  11. Re: Does memory CL timing change when Mhz drops for compatibility?

    AZ Nomad a écrit :
    >
    >>>I wouldn't recomend running either at any clock other than 400mhz.
    >>>Run it too slow and the cells won't be refreshed often enough;

    >
    >>Don't worry about that, the minimum clock speed is much lower that
    >>actual operating speeds. For instance the minimum clock frequency of the
    >>SDRAM chip I mentionned is 1 MHz.

    >
    > That isn't the refresh period.


    Of course not. The maximum refresh period is independent from the clock
    speed, so what is your point about refresh ?

    > That ram will fail if you run it on a 66mhz motherboard.


    Why ?

  12. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Wed, 10 Oct 2007 13:29:52 +0200, Pascal Hambourg wrote:


    >AZ Nomad a écrit :
    >>
    >>>>I wouldn't recomend running either at any clock other than 400mhz.
    >>>>Run it too slow and the cells won't be refreshed often enough;

    >>
    >>>Don't worry about that, the minimum clock speed is much lower that
    >>>actual operating speeds. For instance the minimum clock frequency of the
    >>>SDRAM chip I mentionned is 1 MHz.

    >>
    >> That isn't the refresh period.


    >Of course not. The maximum refresh period is independent from the clock
    >speed, so what is your point about refresh ?

    That the clock speed and refresh are separate issues. Why did you bring up
    the clock speed if you know if is irrelevent?

    >> That ram will fail if you run it on a 66mhz motherboard.


    >Why ?


    The refresh period will be too infrequent.

  13. Re: Does memory CL timing change when Mhz drops for compatibility?

    AZ Nomad a écrit :
    > Pascal Hambourg wrote:
    >
    >>The maximum refresh period is independent from the clock
    >>speed, so what is your point about refresh ?

    >
    > That the clock speed and refresh are separate issues. Why did you bring up
    > the clock speed if you know if is irrelevent?


    I return the question : why did you bring up the refresh while we were
    talking about the clock speed if you know they are separate issues ?

    >>>That ram will fail if you run it on a 66mhz motherboard.

    >
    >>Why ?

    >
    > The refresh period will be too infrequent.


    Why ?

  14. Re: Does memory CL timing change when Mhz drops for compatibility?

    On Thu, 11 Oct 2007 12:27:09 +0200, Pascal Hambourg wrote:


    >AZ Nomad a écrit :
    >> Pascal Hambourg wrote:
    >>
    >>>The maximum refresh period is independent from the clock
    >>>speed, so what is your point about refresh ?

    >>
    >> That the clock speed and refresh are separate issues. Why did you bring up
    >> the clock speed if you know if is irrelevent?


    >I return the question : why did you bring up the refresh while we were
    >talking about the clock speed if you know they are separate issues ?


    >>>>That ram will fail if you run it on a 66mhz motherboard.

    >>
    >>>Why ?

    >>
    >> The refresh period will be too infrequent.


    >Why ?


    faster parts have a shorter refresh period. This has been going on since the
    days when access times were in the hundreds of microseconds.

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