SN54LVT8980A JTAG TAP MASTER help.. - Embedded

This is a discussion on SN54LVT8980A JTAG TAP MASTER help.. - Embedded ; I am currently trying to use the SN54LVT8980A JTAG TAP MASTER controller. I have put the chip on a logic analyzer and have found that I get nothing out (no TDO, no CLK when in gated mode, not TMS) when ...

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Thread: SN54LVT8980A JTAG TAP MASTER help..

  1. SN54LVT8980A JTAG TAP MASTER help..

    I am currently trying to use the SN54LVT8980A JTAG TAP MASTER
    controller. I have put the chip on a logic analyzer and have found
    that I get nothing out (no TDO, no CLK when in gated mode, not TMS)
    when executing a instruction register scan or when I execute a data
    register scan. However, I do get the above mentioned signals when I
    execute either a recirculate instruction scan or a recirculate data
    scan.



    Moreover, I seem to have to write 5 times to the TDO register before
    the STATUS register indicates that it is full.





    Thank you,

    Andy
    acarlisle@acmepacket.com


  2. Re: SN54LVT8980A JTAG TAP MASTER help..

    On 22 Mar 2005 13:38:40 -0800, "heynow567@yahoo.com"
    wrote:

    >I am currently trying to use the SN54LVT8980A JTAG TAP MASTER
    >controller. I have put the chip on a logic analyzer and have found
    >that I get nothing out (no TDO, no CLK when in gated mode, not TMS)
    >when executing a instruction register scan or when I execute a data
    >register scan. However, I do get the above mentioned signals when I
    >execute either a recirculate instruction scan or a recirculate data
    >scan.
    >
    >
    >
    >Moreover, I seem to have to write 5 times to the TDO register before
    >the STATUS register indicates that it is full.
    >

    Are you sure the bus timing to the IC is correct ? If it is marginal,
    then it can account for the type of symptoms you have.

    Regards
    Anton Erasmus



  3. Re: SN54LVT8980A JTAG TAP MASTER help..

    Anton,

    Thanks for the feedback. Have you used this chip before? I would love
    to see a code snippet on how to perform a "instruction-scan", i.e.
    simply shift out a few bits. Likewise, I would like to see a
    "data-scan".

    Thanks,

    Andy
    Anton Erasmus wrote:
    > On 22 Mar 2005 13:38:40 -0800, "heynow567@yahoo.com"
    > wrote:
    >
    > >I am currently trying to use the SN54LVT8980A JTAG TAP MASTER
    > >controller. I have put the chip on a logic analyzer and have found
    > >that I get nothing out (no TDO, no CLK when in gated mode, not TMS)
    > >when executing a instruction register scan or when I execute a data
    > >register scan. However, I do get the above mentioned signals when I
    > >execute either a recirculate instruction scan or a recirculate data
    > >scan.
    > >
    > >
    > >
    > >Moreover, I seem to have to write 5 times to the TDO register before
    > >the STATUS register indicates that it is full.
    > >

    > Are you sure the bus timing to the IC is correct ? If it is marginal,
    > then it can account for the type of symptoms you have.
    >
    > Regards
    > Anton Erasmus



  4. Re: SN54LVT8980A JTAG TAP MASTER help..

    On 23 Mar 2005 12:59:03 -0800, "heynow567@yahoo.com"
    wrote:

    >Anton,
    >
    >Thanks for the feedback. Have you used this chip before? I would love
    >to see a code snippet on how to perform a "instruction-scan", i.e.
    >simply shift out a few bits. Likewise, I would like to see a
    >"data-scan".


    No I have not. I looked at it a year or so ago, but I could only get
    hold of the SN54LVT8980 - Without the A suffix. The A varient
    fixes a couple of nasty bugs on the previous version. From what
    I read, and could remember there was some issues in making sure
    that the bus timing for the chip was correct.

    Regards
    Anton Erasmus



    >Thanks,
    >
    >Andy
    >Anton Erasmus wrote:
    >> On 22 Mar 2005 13:38:40 -0800, "heynow567@yahoo.com"
    >> wrote:
    >>
    >> >I am currently trying to use the SN54LVT8980A JTAG TAP MASTER
    >> >controller. I have put the chip on a logic analyzer and have found
    >> >that I get nothing out (no TDO, no CLK when in gated mode, not TMS)
    >> >when executing a instruction register scan or when I execute a data
    >> >register scan. However, I do get the above mentioned signals when I
    >> >execute either a recirculate instruction scan or a recirculate data
    >> >scan.
    >> >
    >> >
    >> >
    >> >Moreover, I seem to have to write 5 times to the TDO register before
    >> >the STATUS register indicates that it is full.
    >> >

    >> Are you sure the bus timing to the IC is correct ? If it is marginal,
    >> then it can account for the type of symptoms you have.
    >>
    >> Regards
    >> Anton Erasmus



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