VAX floating-point instruction timing? - DEC

This is a discussion on VAX floating-point instruction timing? - DEC ; Peter "Firefly" Lund wrote: > It sounds like stalls would be simpler (but perhaps a bit slower) -- and > then again, no I can see how they could also be more complicated > depending on the microarchitecture. If you ...

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Thread: VAX floating-point instruction timing?

  1. Re: VAX floating-point instruction timing?

    Peter "Firefly" Lund wrote:

    > It sounds like stalls would be simpler (but perhaps a bit slower) -- and
    > then again, no I can see how they could also be more complicated
    > depending on the microarchitecture.


    If you really want to have some entertainment with microcode, acquire access
    to an Integrity server, and learn its assembler -- the Intel IA-64 architecture
    has always reminded me of a superscaler VAX microcode engine. The IAS assembler
    is around and available, and you can acquire a version for OpenVMS or for other
    IA-64 operating systems.







  2. Re: VAX floating-point instruction timing?

    koehler@eisner.nospam.encompasserve.org (Bob Koehler) writes:

    > The 11/785 was rumored to be an 11/780 with the stalls removed,
    > pieces like the massbus adapter had been worked on to handle
    > this.


    The 785 was a 780 re-spun with 74S and 74HS chips.

    "Bug for bug compatable with a 780."

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  3. Re: VAX floating-point instruction timing?

    prep@prep.synonet.com wrote:
    > koehler@eisner.nospam.encompasserve.org (Bob Koehler) writes:
    >
    >> The 11/785 was rumored to be an 11/780 with the stalls removed,
    >> pieces like the massbus adapter had been worked on to handle this.

    >
    > The 785 was a 780 re-spun with 74S and 74HS chips.


    Actually I think you'll find the 785 was a 780 respun with most
    of the 74S (circa 1978) logic replaced with 74F (circa 1983) logic.

    This allowed the cpu clock cycle to be reduced from 200ns to 133ns.

    There were also a few implementation improvements that were applied
    (like larger SRAM availability) that allowed the cache size to be
    increased as well (from 8KB to 32KB).

  4. Re: VAX floating-point instruction timing?

    In article <878xktk1tu.fsf@k9.prep.synonet.com>, prep@prep.synonet.com writes:
    > koehler@eisner.nospam.encompasserve.org (Bob Koehler) writes:
    >
    >> The 11/785 was rumored to be an 11/780 with the stalls removed,
    >> pieces like the massbus adapter had been worked on to handle
    >> this.

    >
    > The 785 was a 780 re-spun with 74S and 74HS chips.
    >
    > "Bug for bug compatable with a 780."


    Yes, but I think the earliest revs of things like the massbus adapter
    couldn't handle what the 74S and 74HS could ask them to do. One
    of the big changes, I think, was an increase to the size of the silo.


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